74F00

QUAD 2-INPUT NAND GATE

Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1980 Fairchild FAST Data Book, page 4-3
Status: Released data sheet
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C

DESCRIPTION

The 74F00 contains four independent 2-input NAND gates in a 14-pin
package.

Logic function (each gate):   Z = /(A * B)

    (output LOW only when both inputs are HIGH)

CONNECTION DIAGRAM (14-pin DIP)

Pin  Function             Pin  Function
---  -------------------  ---  -------------------
  1  A1  gate 1 input      14  Vcc
  2  B1  gate 1 input      13  B4  gate 4 input
  3  Z1  gate 1 output     12  A4  gate 4 input
  4  A2  gate 2 input      11  Z4  gate 4 output
  5  B2  gate 2 input      10  B3  gate 3 input
  6  Z2  gate 2 output      9  A3  gate 3 input
  7  GND                    8  Z3  gate 3 output

TRUTH TABLE (each gate)

 A    B    Z
---  ---  ---
 L    L    H
 L    H    H
 H    L    H
 H    H    L

H = HIGH voltage level;  L = LOW voltage level.

INPUT LOADING / FAN-OUT

Pin Names    Description    U.L. HIGH/LOW
-----------  -------------  -------------
             Inputs         0.5 / 0.375
             Outputs        25 / 12.5

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE

Symbol  Parameter             Min  Typ   Max  Units  Conditions
------  --------------------  ---  ---  ----  -----  ---------------------
ICCH    Power Supply Current             2.8  mA     VIN = Gnd, Vcc = Max
ICCL    Power Supply Current            10.2  mA     VIN = Open, Vcc = Max

AC CHARACTERISTICS

Symbol  Parameter        CL     Min  Typ  Max  Units
------  ---------------  -----  ---  ---  ---  -----
tPLH    Propagation Dly  15 pF  1.5  2.9  3.9  ns
tPLH    Propagation Dly  50 pF  2.0   --  6.0  ns
tPHL    Propagation Dly  15 pF  1.5  2.6  3.6  ns
tPHL    Propagation Dly  50 pF  2.0   --  5.5  ns

Data sheet transcription as plain text

VERILOG MODEL

// ============================================================================
// f00.v — 54F/74F00 Quad 2-Input NAND Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F00.txt (1980 Fairchild FAST Data Book, page 4-3)
//
// Logic function (each gate): Z = ~(A & B)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   A or B to Z   tPLH 2.0 / 6.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f00 (
    input  wire a1, b1,     // gate 1 inputs
    output wire z1,         // gate 1 output
    input  wire a2, b2,     // gate 2 inputs
    output wire z2,         // gate 2 output
    input  wire a3, b3,     // gate 3 inputs
    output wire z3,         // gate 3 output
    input  wire a4, b4,     // gate 4 inputs
    output wire z4          // gate 4 output
);

    assign z1 = ~(a1 & b1);
    assign z2 = ~(a2 & b2);
    assign z3 = ~(a3 & b3);
    assign z4 = ~(a4 & b4);

    specify
        // Propagation delay, A or B to Z (data sheet: tPLH 1.5/2.9/3.9,
        // tPHL 1.5/2.6/3.6 ns)
        specparam tlh = 1.5:2.9:3.9;
        specparam thl = 1.5:2.6:3.6;

        (a1, b1 => z1) = (tlh, thl);
        (a2, b2 => z2) = (tlh, thl);
        (a3, b3 => z3) = (tlh, thl);
        (a4, b4 => z4) = (tlh, thl);
    endspecify

endmodule

f00.v as plain text