DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | MODE SELECT TABLE | INPUT LOADING / FAN-OUT | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
========================================================================
Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1980 Fairchild FAST Data Book, pages 4-31 ... 4-33
(shared data sheet with the 'F163, see 54F74F163.txt)
Status: PRELIMINARY -- page 4-31 carries a "Preliminary" watermark.
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C
The 'F161 and 'F163 are high speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The 'F161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The 'F163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. For dc specifications please refer to the 'F160 data sheet. o SYNCHRONOUS COUNTING AND LOADING o HIGH SPEED SYNCHRONOUS EXPANSION o TYPICAL COUNT FREQUENCY OF 120 MHz
The 'F160 and 'F162 count modulo-10 in the BCD (8421) sequence. From
state 9 (HLLH) they increment to state 0 (LLLL). The 'F161 and 'F163
count modulo-16 in the binary sequence. From state 15 (HHHH) they
increment to state 0 (LLLL).
The clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs (except due to Master
Reset of the 'F160 and 'F161) occur as a result of, and synchronous
with, the LOW-to-HIGH transition of the CP input signal. The circuits
have four fundamental modes of operation, in order of precedence:
asynchronous reset ('F160 and 'F161), synchronous reset ('F162 and
'F163), parallel load, count-up and hold. Five control inputs -- Master
Reset (/MR, 'F160 and 'F161), Synchronous Reset (/SR, 'F162 and 'F163),
Parallel Enable (/PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CET) -- determine the mode of operation, as shown in the Mode
Select Table. A LOW signal on /MR overrides all other inputs and
asynchronously forces all outputs LOW. A LOW signal on /SR overrides
counting and parallel loading and allows all outputs to go LOW on the
next rising edge of CP. A LOW signal on /PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be loaded into
the flip-flops on the next rising edge of CP. With /PE and /MR ('F160,
'F161) or /SR ('F162, 'F163) HIGH, CEP and CET permit counting when
both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits
counting.
The 'F160 - 'F163 use D-type edge-triggered flip-flops and changing the
/SR, /PE, CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is HIGH and the counter
is in its maximum count state (9 for the decade counters, 15 for the
binary counters). To implement synchronous multistage counters, the TC
outputs can be used with the CEP and CET inputs in two different ways.
The TC output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a clock or
asynchronous reset for flip-flops, counters or registers. In the 'F160,
'F162 decade counters, the TC output is fully decoded and can only be
HIGH in state 9. If a decade counter is preset to an illegal state, or
assumes an illegal state when power is applied, it will return to the
normal sequence within two counts, as shown in the state diagram.
Logic equations
~~~~~~~~~~~~~~~
Count Enable = CEP * CET * /PE
('F160, 'F162) TC = Q0 * /Q1 * /Q2 * Q3 * CET
('F161, 'F163) TC = Q0 * Q1 * Q2 * Q3 * CET
State diagram
~~~~~~~~~~~~~
A simple modulo-16 ring -- there are no illegal states:
0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 8 -> 9 -> 10 -> 11 ->
12 -> 13 -> 14 -> 15 -> 0
Pin Function Pin Function --- -------------------------------------- --- -------------------------- 1 /MR Asynchronous Master Reset 16 Vcc 2 CP Clock Pulse (active rising edge) 15 TC Terminal Count output 3 P0 Parallel data input 0 14 Q0 Flip-flop output 0 4 P1 Parallel data input 1 13 Q1 Flip-flop output 1 5 P2 Parallel data input 2 12 Q2 Flip-flop output 2 6 P3 Parallel data input 3 11 Q3 Flip-flop output 3 7 CEP Count Enable Parallel 10 CET Count Enable Trickle 8 GND 9 /PE Parallel Enable
/SR * /PE CET CEP Action on the rising clock edge (^) ----- --- --- --- ----------------------------------- L X X X RESET (Clear) H L X X LOAD (Pn -> Qn) H H H H COUNT (Increment) H H L X NO CHANGE (Hold) H H X L NO CHANGE (Hold) *For the '162 and '163 only. H = HIGH voltage level; L = LOW voltage level; X = immaterial. ^ = LOW-to-HIGH transition of CP.
Pin Names Description U.L. HIGH/LOW
----------- -------------------------------------------- -------------
CEP Count Enable Parallel Input 0.5 / 0.375
CET Count Enable Trickle Input 0.5 / 0.75
CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375
/MR ('F161) Asynchronous Master Reset Input (Active LOW) 0.5 / 0.375
/SR ('F163) Synchronous Reset Input (Active LOW) 0.5 / 0.75
P0 - P3 Parallel Data Inputs 0.5 / 0.375
/PE Parallel Enable Input (Active LOW) 0.5 / 0.75
Q0 - Q3 Flip-flop Outputs 25 / 12.5
TC Terminal Count Output 25 / 12.5
Symbol Parameter Min Typ Max Units
------ ------------------------------------- --- --- --- -----
fmax Maximum Count Frequency 100 120 -- MHz
tPLH Prop Delay CP to Qn (Load Input HIGH) -- 6.0 -- ns
tPHL Prop Delay CP to Qn (Load Input HIGH) -- 7.5 -- ns
tPLH Prop Delay CP to Qn (Load Input LOW) -- 6.0 -- ns
tPHL Prop Delay CP to Qn (Load Input LOW) -- 7.5 -- ns
tPLH Prop Delay CP to TC -- 12 -- ns
tPHL Prop Delay CP to TC -- 8.0 -- ns
tPLH Prop Delay CET to TC -- 6.5 -- ns
tPHL Prop Delay CET to TC -- 6.5 -- ns
tPHL Prop Delay /MR to Qn ('F161) -- 10 -- ns
Symbol Parameter Min Typ Max Units
------ ------------------------------------ --- --- --- -----
ts (H) Setup Time, HIGH -- Pn to CP 5.0 -- -- ns
ts (L) Setup Time, LOW -- Pn to CP 5.0 -- -- ns
th (H) Hold Time, HIGH -- Pn to CP 0 -- -- ns
th (L) Hold Time, LOW -- Pn to CP 0 -- -- ns
ts (H) Setup Time, HIGH -- /PE or /SR to CP 12 -- -- ns
ts (L) Setup Time, LOW -- /PE or /SR to CP 12 -- -- ns
th (H) Hold Time, HIGH -- /PE or /SR to CP 0 -- -- ns
th (L) Hold Time, LOW -- /PE or /SR to CP 0 -- -- ns
ts (H) Setup Time, HIGH -- CEP or CET to CP 9.0 -- -- ns
ts (L) Setup Time, LOW -- CEP or CET to CP 9.0 -- -- ns
th (H) Hold Time, HIGH -- CEP or CET to CP 0 -- -- ns
th (L) Hold Time, LOW -- CEP or CET to CP 0 -- -- ns
tw (H) Clock Pulse Width, HIGH 5.0 -- -- ns
tw (L) Clock Pulse Width, LOW 5.0 -- -- ns
tw (L) /MR Pulse Width LOW ('F161) 10 -- -- ns
trec Recovery Time -- /MR to CP ('F161) 6.0 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f161.v — 54F/74F161 Synchronous Presettable 4-Bit Binary Counter // (Asynchronous Master Reset) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F161.txt (1980 Fairchild FAST Data Book, // pages 4-31 ... 4-33, shared data sheet with the 'F163) // // Modes of operation, in order of precedence (data sheet Mode Select table): // 1. MR_n LOW : asynchronous master reset — all Q // forced LOW immediately, independent // of CP, overriding all other inputs // 2. PE_n LOW : synchronous parallel load of Pn on // the next rising CP edge // 3. MR_n, PE_n HIGH, CEP & CET HIGH : count up on the rising CP edge // 4. CEP or CET LOW : hold // // Count sequence is modulo-16 binary: 0..15, then 15 -> 0 (no illegal // states). // // TC = Q0 & Q1 & Q2 & Q3 & CET — HIGH only in state 15. // // Timing values from the data sheet AC Characteristics table, 54F/74F column // (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). That table lists TYP values // only (the Min/Max columns are blank), so each specparam carries the typ // value alone, as noted per row. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f161 ( input wire mr_n, // master reset (asynchronous, active LOW) input wire cp, // clock pulse (active rising edge) input wire p0, // parallel data input 0 input wire p1, // parallel data input 1 input wire p2, // parallel data input 2 input wire p3, // parallel data input 3 input wire cep, // count enable parallel input wire cet, // count enable trickle input wire pe_n, // parallel enable (active LOW) output wire q0, // flip-flop output 0 output wire q1, // flip-flop output 1 output wire q2, // flip-flop output 2 output wire q3, // flip-flop output 3 output wire tc // terminal count ); // Counter state. All output delays come from the specify block below, // so this model keeps the internal transitions at zero delay. reg [3:0] cnt; always @(posedge cp or negedge mr_n) begin if (!mr_n) cnt <= 4'd0; // asynchronous master reset else if (!pe_n) cnt <= {p3, p2, p1, p0}; // synchronous parallel load else if (cep && cet) cnt <= cnt + 4'd1; // count up, modulo-16 binary // else: CEP or CET LOW — hold end assign q0 = cnt[0]; assign q1 = cnt[1]; assign q2 = cnt[2]; assign q3 = cnt[3]; // Terminal count, data sheet logic equation: // TC = Q0 · Q1 · Q2 · Q3 · CET (HIGH only in state 15) assign tc = cet & cnt[0] & cnt[1] & cnt[2] & cnt[3]; specify // All delays are data-sheet TYP values only: the 54F/74F +25 C, // 5.0 V, C_L = 15 pF AC Characteristics table leaves the Min/Max // columns blank. // Propagation delay CP to Q_n, Load input HIGH (tPLH 6.0, tPHL // 7.5 ns typ); the "Load input LOW" rows list the same values. specparam tlh_cp_q = 6.0; specparam thl_cp_q = 7.5; // Propagation delay CP to TC (tPLH 12, tPHL 8.0 ns typ) specparam tlh_cp_tc = 12.0; specparam thl_cp_tc = 8.0; // Propagation delay CET to TC (tPLH 6.5, tPHL 6.5 ns typ) specparam tlh_cet_tc = 6.5; specparam thl_cet_tc = 6.5; // Propagation delay MR_n to Q_n (tPHL 10 ns typ; MR_n can only // drive Q LOW) specparam thl_mr_q = 10.0; (cp => q0) = (tlh_cp_q, thl_cp_q); (cp => q1) = (tlh_cp_q, thl_cp_q); (cp => q2) = (tlh_cp_q, thl_cp_q); (cp => q3) = (tlh_cp_q, thl_cp_q); (cp => tc) = (tlh_cp_tc, thl_cp_tc); (cet => tc) = (tlh_cet_tc, thl_cet_tc); (mr_n => q0) = (thl_mr_q); (mr_n => q1) = (thl_mr_q); (mr_n => q2) = (thl_mr_q); (mr_n => q3) = (thl_mr_q); // AC operating requirements (data sheet, +25 C 5.0 V minima): // ts(H/L) Pn to CP 5.0, th(H/L) 0; ts(H/L) PE_n to CP 12, th 0; // ts(H/L) CEP/CET to CP 9.0, th 0; tw(H) CP 5.0, tw(L) CP 5.0; // tw(L) MR_n 10; trec MR_n to CP 6.0 ns. // Icarus Verilog does not support timing checks; kept (guarded) // for simulators that do. `ifndef __ICARUS__ specparam ts_p = 5.0; specparam th_p = 0; specparam ts_pe = 12.0; specparam th_pe = 0; specparam ts_ce = 9.0; specparam th_ce = 0; specparam tw_cp_h = 5.0; specparam tw_cp_l = 5.0; specparam tw_mr_l = 10.0; specparam trec_mr = 6.0; $setup(p0, posedge cp, ts_p); $setup(p1, posedge cp, ts_p); $setup(p2, posedge cp, ts_p); $setup(p3, posedge cp, ts_p); $hold(posedge cp, p0, th_p); $hold(posedge cp, p1, th_p); $hold(posedge cp, p2, th_p); $hold(posedge cp, p3, th_p); $setup(pe_n, posedge cp, ts_pe); $hold(posedge cp, pe_n, th_pe); $setup(cep, posedge cp, ts_ce); $setup(cet, posedge cp, ts_ce); $hold(posedge cp, cep, th_ce); $hold(posedge cp, cet, th_ce); $width(posedge cp, tw_cp_h); $width(negedge cp, tw_cp_l); $width(negedge mr_n, tw_mr_l); $recovery(posedge mr_n, posedge cp, trec_mr); `endif endspecify endmodule