DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each flip-flop) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
The 'F175 is a high speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. o Edge-triggered D-type inputs o Buffered positive edge-triggered clock o Asynchronous common reset o True and complement output
The 'F175 consists of four edge-triggered D flip-flops with individual D inputs and Q and /Q outputs. The Clock and Master Reset are COMMON. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individual Q and /Q outputs to follow. A LOW input on the Master Reset (/MR) will force all Q outputs LOW and all /Q outputs HIGH independent of Clock or Data inputs. The 'F175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
Pin Function Pin Function --- ------------------------------ --- ------------------------------ 1 /MR Master Reset (active LOW) 16 Vcc 2 Q0 True output 0 15 Q3 True output 3 3 /Q0 Complement output 0 14 /Q3 Complement output 3 4 D0 Data input 0 13 D3 Data input 3 5 D1 Data input 1 12 D2 Data input 2 6 /Q1 Complement output 1 11 /Q2 Complement output 2 7 Q1 True output 1 10 Q2 True output 2 8 GND 9 CP Clock Pulse (rising edge)
With /MR = H:
Input @ tn Outputs @ tn+1
Dn Qn /Qn
---- ---- ----
L L H
H H L
With /MR = L (asynchronous): all Q = L, all /Q = H, independent of CP
and D.
tn = bit time before the clock positive-going transition;
tn+1 = bit time after the clock positive-going transition.
H = HIGH voltage level; L = LOW voltage level.
Pin Names Description U.L. HIGH/LOW ----------- -------------------------------------- ------------- D0 - D3 Data Inputs 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /MR Master Reset Input (Active LOW) 0.5 / 0.375 Q0 - Q3 True Outputs 25 / 12.5 /Q0 - /Q3 Complement Outputs 25 / 12.5
Test conditions: Vcc = Max, Dn = /MR = 4.5 V, CP = ^ (rising edge) Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 21 mA
Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- fmax Maximum Clock Frequency 110 150 -- MHz tPLH Propagation Delay CP to Qn -- 6.1 -- ns tPHL Propagation Delay CP to Qn -- 6.3 -- ns tPHL Propagation Delay /MR to Qn -- 7.2 -- ns tPLH Propagation Delay /MR to /Qn -- 6.4 -- ns
Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CP 3.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CP 3.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CP 2.0 -- -- ns th (L) Hold Time, LOW -- Dn to CP 2.0 -- -- ns tw (H) CP Pulse Width HIGH 4.5 -- -- ns tw (L) /MR Pulse Width LOW 5.0 -- -- ns trec Recovery Time -- /MR to CP 3.3 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f175.v — 54F/74F175 Quad D Flip-Flop // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F175.txt (1980 Fairchild FAST Data Book, // pages 4-34 ... 4-36; preliminary data sheet) // // Four edge-triggered D flip-flops with individual D inputs and both true // (Q) and complement (Q_n) outputs. Clock (CP) and Master Reset (MR_n) are // common to all four. D is stored on the LOW-to-HIGH CP transition. A LOW // on MR_n forces all Q LOW and all Q_n HIGH, independent of Clock or Data // (asynchronous master reset). // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). // The preliminary data sheet gives TYPICAL values only (Min/Max columns // left blank), so each specparam carries just the typ value. // The data sheet characterizes CP to Q_n only; the CP to Q_n-bar paths // reuse the same values (no separate figures are given for the complement // outputs). MR_n to Q_n is specified tPHL only (Q only falls) and MR_n to // Q_n-bar tPLH only (Q_n-bar only rises), matching the reset direction. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f175 ( input wire mr_n, // master reset (active LOW, asynchronous) input wire cp, // clock pulse (active rising edge) input wire d0, // data input 0 output reg q0, // true output 0 output reg q0_n, // complement output 0 input wire d1, // data input 1 output reg q1, // true output 1 output reg q1_n, // complement output 1 input wire d2, // data input 2 output reg q2, // true output 2 output reg q2_n, // complement output 2 input wire d3, // data input 3 output reg q3, // true output 3 output reg q3_n // complement output 3 ); always @(posedge cp or negedge mr_n) begin if (!mr_n) begin q0 <= 1'b0; q0_n <= 1'b1; end else begin q0 <= d0; q0_n <= ~d0; end end always @(posedge cp or negedge mr_n) begin if (!mr_n) begin q1 <= 1'b0; q1_n <= 1'b1; end else begin q1 <= d1; q1_n <= ~d1; end end always @(posedge cp or negedge mr_n) begin if (!mr_n) begin q2 <= 1'b0; q2_n <= 1'b1; end else begin q2 <= d2; q2_n <= ~d2; end end always @(posedge cp or negedge mr_n) begin if (!mr_n) begin q3 <= 1'b0; q3_n <= 1'b1; end else begin q3 <= d3; q3_n <= ~d3; end end specify // Propagation delay CP to Q_n (data sheet typ only: tPLH 6.1, // tPHL 6.3 ns; min/max blank on preliminary sheet). The sheet // gives no separate CP to Q_n-bar figures; the complement paths // reuse these values (see header note). specparam tlh_cp_q = 6.1; specparam thl_cp_q = 6.3; // Propagation delay MR_n to Q_n, tPHL only (Q only falls on // reset; data sheet typ only: 7.2 ns) specparam thl_mr_q = 7.2; // Propagation delay MR_n to Q_n-bar, tPLH only (Q_n-bar only // rises on reset; data sheet typ only: 6.4 ns) specparam tlh_mr_qn = 6.4; (cp => q0) = (tlh_cp_q, thl_cp_q); (cp => q0_n) = (tlh_cp_q, thl_cp_q); (cp => q1) = (tlh_cp_q, thl_cp_q); (cp => q1_n) = (tlh_cp_q, thl_cp_q); (cp => q2) = (tlh_cp_q, thl_cp_q); (cp => q2_n) = (tlh_cp_q, thl_cp_q); (cp => q3) = (tlh_cp_q, thl_cp_q); (cp => q3_n) = (tlh_cp_q, thl_cp_q); (mr_n => q0) = (thl_mr_q); (mr_n => q1) = (thl_mr_q); (mr_n => q2) = (thl_mr_q); (mr_n => q3) = (thl_mr_q); (mr_n => q0_n) = (tlh_mr_qn); (mr_n => q1_n) = (tlh_mr_qn); (mr_n => q2_n) = (tlh_mr_qn); (mr_n => q3_n) = (tlh_mr_qn); // AC operating requirements (data sheet, +25 C 5.0 V minima): // ts(H) 3.0, ts(L) 3.0, th(H) 2.0, th(L) 2.0, tw(H) CP 4.5, // tw(L) MR_n 5.0, trec 3.3 ns. (The sheet lists no CP LOW pulse // width; fmax 110 min / 150 typ MHz per the AC Characteristics // table.) Icarus Verilog does not support timing checks; kept // (guarded) for simulators that do. `ifndef __ICARUS__ specparam ts_h = 3.0; specparam ts_l = 3.0; specparam th_h = 2.0; specparam th_l = 2.0; specparam tw_cp_h = 4.5; specparam tw_mr_l = 5.0; specparam trec = 3.3; $setup(d0, posedge cp, ts_h); $setup(d1, posedge cp, ts_h); $setup(d2, posedge cp, ts_h); $setup(d3, posedge cp, ts_h); $hold(posedge cp, d0, th_h); $hold(posedge cp, d1, th_h); $hold(posedge cp, d2, th_h); $hold(posedge cp, d3, th_h); $width(posedge cp, tw_cp_h); $width(negedge mr_n, tw_mr_l); $recovery(posedge mr_n, posedge cp, trec); `endif endspecify endmodule