DESCRIPTION | CONNECTION DIAGRAM (14-pin DIP) | TRUTH TABLES | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F242 and 'F243 are quad bus transmitters/receivers designed for 4-line asynchronous 2-way data communications between data buses. o Hysteresis at inputs to improve noise immunity o 2-way asynchronous data bus communication o Input clamp diodes limit high speed termination effects
Pin Function Pin Function --- ------------------- --- ------------------- 1 /E1 Enable input 14 Vcc 2 NC no connection 13 E2 Enable input 3 A1 Bus A, bit 1 12 NC no connection 4 A2 Bus A, bit 2 11 B1 Bus B, bit 1 5 A3 Bus A, bit 3 10 B2 Bus B, bit 2 6 A4 Bus A, bit 4 9 B3 Bus B, bit 3 7 GND 8 B4 Bus B, bit 4 /E1 is the Enable input for one direction (active LOW); E2 is the Enable input for the other direction (active HIGH). Each of the four channels contains a back-to-back pair of inverting 3-state buffers, one enabled by /E1 (A -> B direction) and the other by E2 (B -> A direction). Pins 2 and 12 are no-connect.
/E1 direction (active LOW enable), A -> B ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /E1 D Output --- --- ------ L L H L H L H X Z E2 direction (active HIGH enable), B -> A ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ E2 D Output --- --- ------ L X Z H L H H H L H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance.
Pin Names Description U.L. HIGH/LOW
--------- -------------------------- -------------
/E1 Enable Input (Active LOW) 0.5 / 0.625
E2 Enable Input (Active HIGH) 0.5 / 0.625
Inputs 1.75 / 1.0
Outputs 75 / 40
Test conditions are keyed by number and listed below the table. Symbol Parameter Min Typ Max Units Cond --------- ---------------------------------- ---- --- ---- ----- ---- VOH Output HIGH Voltage 2.4 V (1) VOH Output HIGH Voltage 2.0 V (2) VOH Output HIGH Voltage 2.0 V (3) VOL Output LOW Voltage 0.55 V (4) VOL Output LOW Voltage 0.55 V (5) VT+ - VT- Hysteresis Voltage 0.2 0.4 V (6) IOZH Output OFF Current HIGH 70 uA (7) IOZH Output OFF Current HIGH 100 uA (8) IOZL Output OFF Current LOW -1.6 mA (9) IOS Output Short Circuit Current -100 -225 mA (10) ICC Power Supply Current, outputs HIGH 64 mA (11) ICC Power Supply Current, outputs LOW 64 mA (11) ICC Power Supply Current, outputs OFF 71 mA (11) Conditions (grade shown first where the data sheet gives one): (1) XM, XC: IOH = -3.0 mA, Vcc = Min, VIN = VIH or VIL (2) XM: IOH = -12 mA; VIH = 2.0 V, Vcc = Min, VIL = 0.5 V (3) XC: IOH = -15 mA; VIH = 2.0 V, Vcc = Min, VIL = 0.5 V (4) XM: IOL = 48 mA; VIN = VIH or VIL, Vcc = Min (5) XC: IOL = 64 mA; VIN = VIH or VIL, Vcc = Min (6) Vcc = Min (7) VOUT = 2.7 V; VIN = VIH or VIL, Vcc = Max (8) VOUT = 5.5 V; VIN = VIH or VIL, Vcc = Max (9) Vcc = Max, VIN = VIH or VIL, VOUT = 0.4 V (10) Vcc = Max, VOUT = 0 V (11) Vcc = Max
Symbol Parameter Min Typ Max Units ------ -------------------------------- --- --- --- ----- tPLH Propagation Delay Data to Output -- 6.0 -- ns tPHL Propagation Delay Data to Output -- 6.0 -- ns tPZH Output Enable Time -- 6.0 -- ns tPZL Output Enable Time -- 10 -- ns tPHZ Output Disable Time * -- 10 -- ns tPLZ Output Disable Time * -- 6.0 -- ns * Disable times measured with CL = 5.0 pF, RL = 90 ohms.
Data sheet transcription as plain text
// ============================================================================ // f242.v — 54F/74F242 Quad Bus Transceiver, Inverting (3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F242.txt (1980 Fairchild FAST Data Book, // pages 4-70 ... 4-72; shared data sheet with 'F243, preliminary) // // Four channels, each a back-to-back pair of INVERTING 3-state buffers // between the bidirectional bus pins A1..A4 and B1..B4: // A -> B direction enabled by E1_n LOW (active LOW); // B -> A direction enabled by E2 HIGH (active HIGH). // Data is inverted in both directions. // // Truth tables (per channel): // E1_n=L, A=L -> B=H; E1_n=L, A=H -> B=L; E1_n=H -> B=Z. // E2=H, B=L -> A=H; E2=H, B=H -> A=L; E2=L -> A=Z. // // The transcribed data sheet (docs/devices/54F74F242.txt) does not warn // against enabling both directions at once — the two truth tables are // printed independently, with no combined row. This model does not model // that case either: with both enabled, each bus pin would have two active // drivers forming an inverting feedback loop (B = ~A while A = ~B), which // is left unresolved rather than guessed at. // // On real hardware this is dangerous, not merely unspecified: a Philips // datasheet for the same industry-standard part (not this project's // Fairchild source) states the both-enabled condition is "not allowed due // to excessive currents" — two active totem-pole outputs fighting each // other continuously, which this model has no way to represent. The later // 'F245/'F545/'F588 transceivers replace the two independent enables with // a single T//R direction-select line, making the condition structurally // impossible rather than merely forbidden; 'F242/'F243 are the outliers // in this family for carrying the hazard at all. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), in ns. // The preliminary data sheet lists TYPICAL values only (Min/Max columns // left blank), so the specparams below are typ-only single values. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. Each bus pin is a path // DESTINATION in one direction and a SOURCE in the other, so the specify // block carries one statement per scalar pin per direction. // ============================================================================ `timescale 1ns/100ps module f242 ( input wire e1_n, // enable, A -> B direction (active LOW) input wire e2, // enable, B -> A direction (active HIGH) inout wire a1, a2, a3, a4, // bus A (bidirectional) inout wire b1, b2, b3, b4 // bus B (bidirectional) ); // A -> B (inverting), enabled by E1_n LOW assign b1 = e1_n ? 1'bz : ~a1; assign b2 = e1_n ? 1'bz : ~a2; assign b3 = e1_n ? 1'bz : ~a3; assign b4 = e1_n ? 1'bz : ~a4; // B -> A (inverting), enabled by E2 HIGH assign a1 = e2 ? ~b1 : 1'bz; assign a2 = e2 ? ~b2 : 1'bz; assign a3 = e2 ? ~b3 : 1'bz; assign a4 = e2 ? ~b4 : 1'bz; specify // Data sheet AC Characteristics (preliminary: typ values only, // min/max columns blank), C_L = 15 pF; disable times measured with // C_L = 5.0 pF, R_L = 90 ohm: // tPLH = 6.0, tPHL = 6.0 (Propagation Delay Data to Output) // tPZH = 6.0, tPZL = 10 (Output Enable Time) // tPHZ = 10, tPLZ = 6.0 (Output Disable Time) specparam tlh = 6.0; // tPLH, data to output specparam thl = 6.0; // tPHL, data to output specparam tlz = 6.0; // tPLZ, output disable (0 -> Z) specparam tzh = 6.0; // tPZH, output enable (Z -> 1) specparam thz = 10.0; // tPHZ, output disable (1 -> Z) specparam tzl = 10.0; // tPZL, output enable (Z -> 0) // A -> B direction: bus B pins are the path destinations (a1, e1_n => b1) = (tlh, thl, tlz, tzh, thz, tzl); (a2, e1_n => b2) = (tlh, thl, tlz, tzh, thz, tzl); (a3, e1_n => b3) = (tlh, thl, tlz, tzh, thz, tzl); (a4, e1_n => b4) = (tlh, thl, tlz, tzh, thz, tzl); // B -> A direction: the same physical pins, opposite roles — // bus A pins are the path destinations (b1, e2 => a1) = (tlh, thl, tlz, tzh, thz, tzl); (b2, e2 => a2) = (tlh, thl, tlz, tzh, thz, tzl); (b3, e2 => a3) = (tlh, thl, tlz, tzh, thz, tzl); (b4, e2 => a4) = (tlh, thl, tlz, tzh, thz, tzl); endspecify endmodule