DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS | VERILOG MODEL
The 'F374 is a high speed, low power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (/OE) are common to all flip-flops. o EDGE-TRIGGERED D-TYPE INPUTS o BUFFERED POSITIVE EDGE-TRIGGERED CLOCK o 3-STATE OUTPUTS FOR BUS ORIENTED APPLICATIONS
The 'F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (/OE) LOW, the contents of the eight flip-flops are available at the outputs. When /OE is HIGH, the outputs go to the high impedance state. Operation of the /OE input does not affect the state of the flip-flops.
Pin Function Pin Function
--- -------------------------- --- -------------------------------------
1 /OE 3-State Output Enable 20 Vcc
(active LOW)
2 O0 Output 0 19 O7 Output 7
3 D0 Data input 0 18 D7 Data input 7
4 D1 Data input 1 17 D6 Data input 6
5 O1 Output 1 16 O6 Output 6
6 O2 Output 2 15 O5 Output 5
7 D2 Data input 2 14 D5 Data input 5
8 D3 Data input 3 13 D4 Data input 4
9 O3 Output 3 12 O4 Output 4
10 GND 11 CP Clock Pulse (active rising edge)
Dn CP /OE On --- --- --- --- H ^ L H L ^ L L X X H Z H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance; ^ = LOW-to-HIGH clock transition.
Pin Names Description U.L. HIGH/LOW --------- ---------------------------------------- ------------- D0 - D7 Data Inputs 0.5 / 0.375 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375 O0 - O7 3-State Outputs 25 / 12.5
Conditions for all rows: Vcc = Max, Dn = Gnd, /OE = 4.5 V. Symbol Parameter Min Typ Max Units ------ -------------------------------------- --- --- --- ----- ICC Power Supply Current (All Outputs OFF) 55 86 mA
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- fmax Maximum Clock Frequency -- -- -- MHz tPLH Propagation Delay CP to On 3.0 5.5 9.0 ns tPHL Propagation Delay CP to On 3.0 5.5 9.0 ns tPZH Output Enable Time 3.0 6.5 10 ns tPZL Output Enable Time 3.0 6.5 10 ns tPHZ Output Disable Time (1) 3.0 5.5 8.0 ns tPLZ Output Disable Time (1) 3.0 4.5 7.0 ns (1) Disable times measured with CL = 5 pF.
Symbol Parameter Min Typ Max Units ------ ---------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CP 2.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CP 2.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CP 2.0 -- -- ns th (L) Hold Time, LOW -- Dn to CP 2.0 -- -- ns tw (H) CP Pulse Width, HIGH 7.0 -- -- ns tw (L) CP Pulse Width, LOW 6.0 -- -- ns
Data sheet transcription as plain text
// ============================================================================ // f374.v — 54F/74F374 Octal D-Type Flip-Flop (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F374.txt (1980 Fairchild FAST Data Book, // pages 4-103 ... 4-104) // // Eight edge-triggered D-type flip-flops with 3-state true outputs. The // flip-flops store the state of their D inputs on the LOW-to-HIGH Clock // (CP) transition. Output Enable (OE_n) LOW drives the outputs; OE_n HIGH // forces the high-impedance state without affecting the flip-flops. // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // The data sheet f_max row was printed with no values; not modeled. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f374 ( input wire oe_n, // 3-state output enable (active LOW) input wire cp, // clock pulse (active rising edge) input wire d0, d1, d2, d3, // data inputs 0-3 input wire d4, d5, d6, d7, // data inputs 4-7 output wire o0, o1, o2, o3, // 3-state outputs 0-3 output wire o4, o5, o6, o7 // 3-state outputs 4-7 ); // Edge-triggered flip-flop bank: D stored on the rising CP edge. reg [7:0] q_int; always @(posedge cp) begin q_int <= {d7, d6, d5, d4, d3, d2, d1, d0}; end // 3-state output buffers (OE_n HIGH -> high impedance) assign o0 = oe_n ? 1'bz : q_int[0]; assign o1 = oe_n ? 1'bz : q_int[1]; assign o2 = oe_n ? 1'bz : q_int[2]; assign o3 = oe_n ? 1'bz : q_int[3]; assign o4 = oe_n ? 1'bz : q_int[4]; assign o5 = oe_n ? 1'bz : q_int[5]; assign o6 = oe_n ? 1'bz : q_int[6]; assign o7 = oe_n ? 1'bz : q_int[7]; specify // Propagation delay CP to O_n (data sheet: tPLH 3.0/5.5/9.0, // tPHL 3.0/5.5/9.0 ns) specparam tlh_cp_o = 3.0:5.5:9.0; specparam thl_cp_o = 3.0:5.5:9.0; // Output enable/disable time OE_n to O_n (data sheet: // tPZH 3.0/6.5/10, tPZL 3.0/6.5/10, tPHZ 3.0/5.5/8.0, // tPLZ 3.0/4.5/7.0 ns; disable times measured with C_L = 5 pF) specparam tzh_oe_o = 3.0:6.5:10; specparam tzl_oe_o = 3.0:6.5:10; specparam thz_oe_o = 3.0:5.5:8.0; specparam tlz_oe_o = 3.0:4.5:7.0; // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0): // CP causes only 0->1/1->0 transitions, OE_n only Z transitions. (oe_n, cp => o0) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o1) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o2) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o3) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o4) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o5) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o6) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oe_n, cp => o7) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); // AC operating requirements (data sheet, +25 C 5.0 V minima): // ts(H) 2.0, ts(L) 2.0, th(H) 2.0, th(L) 2.0, tw(H) CP 7.0, // tw(L) CP 6.0 ns. Icarus Verilog does not support timing checks; // kept (guarded) for simulators that do. `ifndef __ICARUS__ specparam ts_h = 2.0; specparam ts_l = 2.0; specparam th_h = 2.0; specparam th_l = 2.0; specparam tw_cp_h = 7.0; specparam tw_cp_l = 6.0; $setup(d0, posedge cp, ts_h); $setup(d1, posedge cp, ts_h); $setup(d2, posedge cp, ts_h); $setup(d3, posedge cp, ts_h); $setup(d4, posedge cp, ts_h); $setup(d5, posedge cp, ts_h); $setup(d6, posedge cp, ts_h); $setup(d7, posedge cp, ts_h); $hold(posedge cp, d0, th_h); $hold(posedge cp, d1, th_h); $hold(posedge cp, d2, th_h); $hold(posedge cp, d3, th_h); $hold(posedge cp, d4, th_h); $hold(posedge cp, d5, th_h); $hold(posedge cp, d6, th_h); $hold(posedge cp, d7, th_h); $width(posedge cp, tw_cp_h); $width(negedge cp, tw_cp_l); `endif endspecify endmodule