DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | TRUTH TABLE (each half) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F539 contains two independent decoders. Each accepts two Address (A0, A1) input signals and decodes them to select one of four mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active-HIGH (P = L) or active-LOW (P = H). An active-LOW input Enable (/E) is available for data demultiplexing; data is routed to the selected output in non-inverted form in the active-LOW mode or in inverted form in the active-HIGH mode. A HIGH signal on the active-LOW Output Enable (/OE) input forces the 3-state outputs to the high impedance state.
Pin Function Pin Function --- ------------------------------- --- ------------------------------- 1 O2b Side B Output 2 20 Vcc 2 O1b Side B Output 1 19 O3b Side B Output 3 3 O0b Side B Output 0 18 A1b Side B Address input 1 4 Pb Side B Polarity Control 17 A0b Side B Address input 0 5 /OEb Side B Output Enable (LOW) 16 /Eb Side B Enable (active LOW) 6 A0a Side A Address input 0 15 /Ea Side A Enable (active LOW) 7 A1a Side A Address input 1 14 /OEa Side A Output Enable (LOW) 8 O3a Side A Output 3 13 Pa Side A Polarity Control 9 O2a Side A Output 2 12 O0a Side A Output 0 10 GND 11 O1a Side A Output 1
H = HIGH voltage level; L = LOW voltage level; X = immaterial;
Z = high impedance state.
Function /OE /E A1 A0 O0 O1 O2 O3
-------------- --- -- -- -- -- -- -- --
High Impedance H X X X Z Z Z Z
Disable L H X X On = P
Active-HIGH L L L L H L L L
Output L L L H L H L L
(P = L) L L H L L L H L
L L H H L L L H
Active-LOW L L L L L H H H
Output L L L H H L H H
(P = H) L L H L H H L H
L L H H H H H L
Pin Names Description U.L. HIGH/LOW ----------- -------------------------------- ------------- A0a - A1a Side A Address Inputs 0.5 / 0.375 A0b - A1b Side B Address Inputs 0.5 / 0.375 /Ea, /Eb Enable Inputs (Active LOW) 0.5 / 0.375 /OEa, /OEb Output Enable Inputs (Active LOW) 0.5 / 0.375 Pa, Pb Polarity Control Inputs 0.5 / 0.375 O0a - O3a Side A 3-State Outputs 25 / 12.5 O0b - O3b Side B 3-State Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units ------ -------------------------------------- --- --- --- ----- ICC Power Supply Current (All Outputs OFF) 42 mA Conditions: A0, A1, /E = Gnd; /OE, P = HIGH. (Printed as a single row; not broken out per side on the data sheet.)
Symbol Parameter Min Typ Max Units ------ --------------------------------- --- ---- --- ----- tPLH Propagation Delay An to On -- 12.5 -- ns tPHL Propagation Delay An to On -- 11.5 -- ns tPLH Propagation Delay /E to On -- 11.5 -- ns tPHL Propagation Delay /E to On -- 11 -- ns tPLH Propagation Delay P to On -- 13 -- ns tPHL Propagation Delay P to On -- 12 -- ns tPZH Output Enable Time /OE to On -- 5.0 -- ns tPZL Output Enable Time /OE to On -- 5.5 -- ns tPHZ Output Disable Time (1) /OE to On -- 5.0 -- ns tPLZ Output Disable Time (1) /OE to On -- 5.0 -- ns (1) Disable times measured with CL = 5.0 pF.
Data sheet transcription as plain text
// ============================================================================ // f539.v — 54F/74F539 Dual 1-of-4 Decoder (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F539.txt (1980 Fairchild FAST Data Book, // pages 4-118 ... 4-120) — PRELIMINARY data sheet. // // Two independent one-of-four decoders, each with two active-HIGH address // inputs and four mutually exclusive 3-state outputs. // - Polarity control P: P = L -> active-HIGH outputs (selected output // HIGH, others LOW); P = H -> active-LOW outputs (selected output LOW, // others HIGH). // - Enable E_n active LOW; when HIGH all four outputs of that half equal // the P input, so E_n serves as the data input when demultiplexing. // - OE_n HIGH forces that half's outputs to the high-impedance state. // // Suffixes a and b name the two halves, matching the data sheet pin names. // // Timing values from the data sheet AC Characteristics table // (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The preliminary sheet gives // TYP ONLY (min/max columns blank). // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f539 ( input wire a0a, a1a, // side A address inputs (active HIGH) input wire ea_n, // side A enable input (active LOW) input wire oea_n, // side A output enable (active LOW) input wire pa, // side A polarity control input output wire o0a, o1a, o2a, o3a, // side A 3-state outputs 0-3 input wire a0b, a1b, // side B address inputs (active HIGH) input wire eb_n, // side B enable input (active LOW) input wire oeb_n, // side B output enable (active LOW) input wire pb, // side B polarity control input output wire o0b, o1b, o2b, o3b // side B 3-state outputs 0-3 ); wire [3:0] dec_a, dec_b; // One-hot decode, gated by the active-LOW enable. Each output is the // AND of both address bits against its own code (matching f138/f139's // construction) rather than a single indexed bit-select write: an // indexed write with an x-valued address index (`dec_a[addr_a] = 1'b1`) // is silently dropped by Verilog's bit-select semantics, which would // read as "disabled" instead of propagating the x. Written this way, an // x on an address bit only reaches the (at most two) outputs whose code // still matches the known bits. assign dec_a[0] = ~ea_n & ~a1a & ~a0a; assign dec_a[1] = ~ea_n & ~a1a & a0a; assign dec_a[2] = ~ea_n & a1a & ~a0a; assign dec_a[3] = ~ea_n & a1a & a0a; assign dec_b[0] = ~eb_n & ~a1b & ~a0b; assign dec_b[1] = ~eb_n & ~a1b & a0b; assign dec_b[2] = ~eb_n & a1b & ~a0b; assign dec_b[3] = ~eb_n & a1b & a0b; // Polarity control (XOR): selected output is ~P, all others P. // OE_n HIGH forces the high-impedance state. assign o0a = oea_n ? 1'bz : (dec_a[0] ^ pa); assign o1a = oea_n ? 1'bz : (dec_a[1] ^ pa); assign o2a = oea_n ? 1'bz : (dec_a[2] ^ pa); assign o3a = oea_n ? 1'bz : (dec_a[3] ^ pa); assign o0b = oeb_n ? 1'bz : (dec_b[0] ^ pb); assign o1b = oeb_n ? 1'bz : (dec_b[1] ^ pb); assign o2b = oeb_n ? 1'bz : (dec_b[2] ^ pb); assign o3b = oeb_n ? 1'bz : (dec_b[3] ^ pb); specify // Propagation delay A_n to O_n (data sheet, TYP ONLY — preliminary // sheet, min/max blank: tPLH 12.5, tPHL 11.5 ns) specparam tlh_a_o = 12.5; specparam thl_a_o = 11.5; // Propagation delay E_n to O_n (data sheet, TYP ONLY: tPLH 11.5, // tPHL 11 ns) specparam tlh_e_o = 11.5; specparam thl_e_o = 11.0; // Propagation delay P to O_n (data sheet, TYP ONLY: tPLH 13, // tPHL 12 ns) specparam tlh_p_o = 13.0; specparam thl_p_o = 12.0; // Output enable/disable time OE_n to O_n (data sheet, TYP ONLY: // tPZH 5.0, tPZL 5.5, tPHZ 5.0, tPLZ 5.0 ns; disable times // measured with C_L = 5 pF) specparam tzh_oe_o = 5.0; specparam tzl_oe_o = 5.5; specparam thz_oe_o = 5.0; specparam tlz_oe_o = 5.0; (a0a, a1a => o0a) = (tlh_a_o, thl_a_o); (a0a, a1a => o1a) = (tlh_a_o, thl_a_o); (a0a, a1a => o2a) = (tlh_a_o, thl_a_o); (a0a, a1a => o3a) = (tlh_a_o, thl_a_o); (ea_n => o0a) = (tlh_e_o, thl_e_o); (ea_n => o1a) = (tlh_e_o, thl_e_o); (ea_n => o2a) = (tlh_e_o, thl_e_o); (ea_n => o3a) = (tlh_e_o, thl_e_o); // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0): // P causes only 0->1/1->0 transitions, OE_n only Z transitions. (oea_n, pa => o0a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oea_n, pa => o1a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oea_n, pa => o2a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oea_n, pa => o3a) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (a0b, a1b => o0b) = (tlh_a_o, thl_a_o); (a0b, a1b => o1b) = (tlh_a_o, thl_a_o); (a0b, a1b => o2b) = (tlh_a_o, thl_a_o); (a0b, a1b => o3b) = (tlh_a_o, thl_a_o); (eb_n => o0b) = (tlh_e_o, thl_e_o); (eb_n => o1b) = (tlh_e_o, thl_e_o); (eb_n => o2b) = (tlh_e_o, thl_e_o); (eb_n => o3b) = (tlh_e_o, thl_e_o); (oeb_n, pb => o0b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oeb_n, pb => o1b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oeb_n, pb => o2b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); (oeb_n, pb => o3b) = (tlh_p_o, thl_p_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o); endspecify endmodule