DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (20-pin DIP) | MODE SELECT TABLE | /CC TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | AC OPERATING REQUIREMENTS
========================================================================
Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1985 Fairchild FAST Data Book, pages 4-451 ... 4-457
(shared data sheet with the 'F568, see 54F74F568.txt). The 1980
data book carries the 'F569 in its Section 3 selection guide
only (page 3-25, description and logic symbol).
Status: Released data sheet
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C
The 'F568 and 'F569 are fully synchronous, reversible counters with 3-state outputs. The 'F568 is a BCD decade counter; the 'F569 is a binary counter. They feature preset capability for programmable operation, carry lookahead for easy cascading, and a U//D input to control the direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (/CC) and Terminal Count (/TC) outputs. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable (/OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. o Synchronous Counting and Loading o Lookahead Carry Capability for Easy Cascading o Preset Capability for Programmable Operation o 3-State Outputs for Bus Organized Systems
The 'F568 counts modulo-10 in the BCD (8421) sequence. From state 9
(HLLH) it will increment to 0 (LLLL) in the Up mode; in Down mode it
will decrement from 0 to 9. The 'F569 counts in the modulo-16 binary
sequence. From state 15 it will increment to state 0 in the Up mode; in
the Down mode it will decrement from 0 to 15. The clock inputs of all
flip-flops are driven in parallel through a clock buffer. All state
changes (except due to Master Reset) occur synchronously with the
LOW-to-HIGH transition of the Clock Pulse (CP) input signal.
The circuits have five fundamental modes of operation, in order of
precedence: asynchronous reset, synchronous reset, parallel load, count
and hold. Five control inputs -- Master Reset (/MR), Synchronous Reset
(/SR), Parallel Enable (/PE), Count Enable Parallel (/CEP) and Count
Enable Trickle (/CET) -- plus the Up/Down (U//D) input, determine the
mode of operation, as shown in the Mode Select Table. A LOW signal on
/MR overrides all other inputs and asynchronously forces the flip-flop Q
outputs LOW. A LOW signal on /SR overrides counting and parallel loading
and allows the Q outputs to go LOW on the next rising edge of CP. A LOW
signal on /PE overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip-flops on the next rising
edge of CP. With /MR, /SR and /PE HIGH, /CEP and /CET permit counting
when both are LOW. Conversely, a HIGH signal on either /CEP or /CET
inhibits counting.
The 'F568 and 'F569 use edge-triggered flip-flops and changing the /SR,
/PE, /CEP, /CET or U//D inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold times, with
respect to the rising edge of CP, are observed.
Two types of outputs are provided as overflow/underflow indicators. The
Terminal Count (/TC) output is normally HIGH and goes LOW providing /CET
is LOW, when the counter reaches zero in the Down mode, or reaches
maximum (9 for the 'F568, 15 for the 'F569) in the Up mode. /TC will
then remain LOW until a state change occurs, whether by counting or
presetting, or until U//D or /CET is changed. To implement synchronous
multistage counters, the connections between the /TC output and the /CEP
and /CET inputs can provide either slow or fast carry propagation.
Figure a shows the connections for simple ripple carry, in which the
clock period must be longer than the CP to /TC delay of the first stage,
plus the cumulative /CET to /TC delays of the intermediate stages, plus
the /CET to CP setup time of the last stage. This total delay plus setup
time sets the upper limit on clock frequency. For faster clock rates,
the carry lookahead connections shown in Figure b are recommended. In
this scheme the ripple delay through the intermediate stages commences
with the same clock that causes the first stage to tick over from max to
min in the Up mode, or min to max in the Down mode, to start its final
cycle. Since this final cycle takes 10 ('F568) or 16 ('F569) clocks to
complete, there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock period is
the CP to /TC delay of the first stage plus the /CEP to CP setup time of
the last stage. The /TC output is subject to decoding spikes due to
internal race conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or counters. For
such applications, the Clocked Carry (/CC) output is provided. The /CC
output is normally HIGH. When /CEP, /CET, and /TC are LOW, the /CC
output will go LOW when the clock next goes LOW and will stay LOW until
the clock goes HIGH again, as shown in the /CC Truth Table. When the
Output Enable (/OE) is LOW, the parallel data outputs O0-O3 are active
and follow the flip-flop Q outputs. A HIGH signal on /OE forces O0-O3 to
the High Z state but does not prevent counting, loading or resetting.
Logic equations
~~~~~~~~~~~~~~~
Count Enable = /CEP * /CET * PE
Up ('F568): /TC = Q0 * /Q1 * /Q2 * Q3 * (Up) * /CET
('F569): /TC = Q0 * Q1 * Q2 * Q3 * (Up) * /CET
Down (Both): /TC = /Q0 * /Q1 * /Q2 * /Q3 * (Down) * /CET
State diagram
~~~~~~~~~~~~~
Count Up: 0 -> 1 -> 2 -> ... -> 14 -> 15 -> 0.
Count Down: 0 -> 15 -> 14 -> ... -> 2 -> 1 -> 0.
All sixteen states are legitimate, so the 'F569 has no illegal-state
recovery paths.
Pin Function Pin Function --- ----------------------------- --- --------------------------- 1 U//D Up/Down Count Control 20 Vcc 2 CP Clock Pulse 19 /TC Terminal Count output 3 P0 Parallel data input 0 18 /CC Clocked Carry output 4 P1 Parallel data input 1 17 /OE Output Enable 5 P2 Parallel data input 2 16 O0 Data output 0 6 P3 Parallel data input 3 15 O1 Data output 1 7 /CEP Count Enable Parallel 14 O2 Data output 2 8 /MR Master Reset 13 O3 Data output 3 9 /SR Synchronous Reset 12 /CET Count Enable Trickle 10 GND 11 /PE Parallel Enable CP is active on the rising edge of the clock.
Inputs ------------------------------------ /MR /SR /PE /CEP /CET U//D Operating Mode --- --- --- ---- ---- ---- -------------------- L X X X X X Asynchronous Reset H L X X X X Synchronous Reset H H L X X X Parallel Load H H H H X X Hold H H H X H X Hold H H H L L H Count Up H H H L L L Count Down H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Inputs Output
------------------------------------- ------
/SR /PE /CEP /CET /TC* CP /CC
--- --- ---- ---- ---- ----- ------
L X X X X X H
X L X X X X H
X X H X X X H
X X X H X X H
X X X X H X H
H H L L L Pulse Pulse
* /TC is generated internally.
H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Pulse = /CC goes LOW when the clock next goes LOW and stays LOW until
the clock goes HIGH again.
Pin Names Description U.L. HIGH/LOW ---------- ---------------------------------------- ------------- P0 - P3 Parallel Data Inputs 0.5 / 0.375 /CEP Count Enable Parallel Input (Active LOW) 0.5 / 0.375 /CET Count Enable Trickle Input (Active LOW) 0.5 / 0.75 CP Clock Pulse Input (Active Rising Edge) 0.5 / 0.375 /PE Parallel Enable Input (Active LOW) 0.5 / 0.75 U//D Up/Down Count Control Input 0.5 / 0.375 /OE Output Enable Input (Active LOW) 0.5 / 0.375 /MR Master Reset Input (Active LOW) 0.5 / 0.375 /SR Synchronous Reset Input (Active LOW) 0.5 / 0.375 O0 - O3 3-State Parallel Data Outputs 75 / 25 /TC Terminal Count Output (Active LOW) 25 / 12.5 /CC Clocked Carry Output (Active LOW) 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 45 67 mA Vcc = Max
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ------------------------------- ----- --- ---- ---- --- ---- -----
fmax Maximum Clock Frequency -- 100 115 -- 90 -- MHz
tPLH Prop Delay CP to On 50 pF 3.0 6.5 8.5 3.0 9.5 ns
(/PE HIGH or LOW)
tPHL Prop Delay CP to On 50 pF 4.0 9.0 11.5 4.0 13.0 ns
(/PE HIGH or LOW)
tPLH Prop Delay CP to /TC 50 pF 5.5 12.0 15.5 5.5 17.5 ns
tPHL Prop Delay CP to /TC 50 pF 4.0 8.5 11.0 4.0 12.5 ns
tPLH Prop Delay /CET to /TC 50 pF 2.5 4.5 6.0 2.5 7.0 ns
tPHL Prop Delay /CET to /TC 50 pF 2.5 6.0 8.0 2.5 9.0 ns
tPLH Prop Delay U//D to /TC ('F569) 50 pF 3.5 8.5 11.0 3.5 12.5 ns
tPHL Prop Delay U//D to /TC ('F569) 50 pF 4.0 8.0 10.5 4.0 12.0 ns
tPLH Prop Delay CP to /CC 50 pF 2.5 5.5 7.0 2.5 8.0 ns
tPHL Prop Delay CP to /CC 50 pF 2.0 4.5 6.0 2.0 7.0 ns
tPLH Prop Delay /CEP, /CET to /CC 50 pF 2.5 5.0 6.5 2.5 7.5 ns
tPHL Prop Delay /CEP, /CET to /CC 50 pF 4.0 8.5 11.0 4.0 12.5 ns
tPHL Prop Delay /MR to On 50 pF 5.0 10.0 13.0 5.0 14.5 ns
tPZH Output Enable Time /OE to On 50 pF 2.5 5.5 7.0 2.5 8.0 ns
tPZL Output Enable Time /OE to On 50 pF 3.0 6.0 3.0 3.0 9.0 ns
tPHZ Output Disable Time /OE to On 50 pF 1.5 5.0 6.5 1.5 7.5 ns
tPLZ Output Disable Time /OE to On 50 pF 2.0 4.5 6.0 2.0 7.0 ns
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter Min Typ Max Min Max Units
------ --------------------------------------- --- --- --- --- --- -----
ts (H) Setup Time, HIGH -- Pn to CP 4.0 -- -- 4.5 -- ns
ts (L) Setup Time, LOW -- Pn to CP 4.0 -- -- 4.5 -- ns
th (H) Hold Time, HIGH -- Pn to CP 3.0 -- -- 3.5 -- ns
th (L) Hold Time, LOW -- Pn to CP 3.0 -- -- 3.5 -- ns
ts (H) Setup Time, HIGH -- /CEP or /CET to CP 5.0 -- -- 6.0 -- ns
ts (L) Setup Time, LOW -- /CEP or /CET to CP 5.0 -- -- 6.0 -- ns
th (H) Hold Time, HIGH -- /CEP or /CET to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /CEP or /CET to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- /PE to CP 8.0 -- -- 9.0 -- ns
ts (L) Setup Time, LOW -- /PE to CP 8.0 -- -- 9.0 -- ns
th (H) Hold Time, HIGH -- /PE to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /PE to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- U//D to CP ('F569) 11.0 -- -- 12.5 -- ns
ts (L) Setup Time, LOW -- U//D to CP ('F569) 7.0 -- -- 8.0 -- ns
th (H) Hold Time, HIGH -- U//D to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- U//D to CP 0 -- -- 0 -- ns
ts (H) Setup Time, HIGH -- /SR to CP 9.5 -- -- 10.5 -- ns
ts (L) Setup Time, LOW -- /SR to CP 8.5 -- -- 9.5 -- ns
th (H) Hold Time, HIGH -- /SR to CP 0 -- -- 0 -- ns
th (L) Hold Time, LOW -- /SR to CP 0 -- -- 0 -- ns
tw (H) CP Pulse Width, HIGH 4.0 -- -- 4.5 -- ns
tw (L) CP Pulse Width, LOW 6.0 -- -- 6.5 -- ns
tw (L) /MR Pulse Width, LOW 4.5 -- -- 5.0 -- ns
trec /MR Recovery Time 6.0 -- -- 7.0 -- ns
Data sheet transcription as plain text
No model for this device yet — only the data sheet transcription above.