74F64

4-2-3-2-INPUT AND-OR-INVERT GATE

Family: Fairchild FAST (Advanced Schottky TTL)
Source: 1980 Fairchild FAST Data Book, page 4-11
Status: PRELIMINARY -- the data sheet page carries a "Preliminary" watermark.
Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C

DESCRIPTION

The 74F64 is a single AND-OR-Invert gate with four AND groups of 4, 2, 3
and 2 inputs respectively, whose outputs are OR-ed and inverted to
produce one output.

Logic function:   Z = /[(A*B*C*D) + (E*F) + (G*H*I) + (J*K)]

CONNECTION DIAGRAM (14-pin DIP)

Pin  Function             Pin  Function
---  -------------------  ---  -------------------
  1  A  4-input group      14  Vcc
  2  E  2-input group      13  D  4-input group
  3  F  2-input group      12  C  4-input group
  4  G  3-input group      11  B  4-input group
  5  H  3-input group      10  K  2-input group
  6  I  3-input group       9  J  2-input group
  7  GND                    8  Z  output

Group membership traced from the connection diagram:

AND group  Width  Pins
---------  -----  -------------
A*B*C*D    4      1, 11, 12, 13
E*F        2      2, 3
G*H*I      3      4, 5, 6
J*K        2      9, 10

TRUTH TABLE

The output Z is LOW when ANY AND group has all of its inputs HIGH;
otherwise Z is HIGH.

Condition       Z
--------------  -
A*B*C*D = H     L
E*F = H         L
G*H*I = H       L
J*K = H         L
all groups L    H

H = HIGH voltage level;  L = LOW voltage level.

INPUT LOADING / FAN-OUT

Pin Names    Description    U.L. HIGH/LOW
-----------  -------------  -------------
             Inputs         0.5 / 0.375
             Outputs        25 / 12.5

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE

Symbol  Parameter             Min  Typ   Max  Units  Conditions
------  --------------------  ---  ---  ----  -----  ---------------------
ICCH    Power Supply Current             2.8  mA     VIN = Gnd, Vcc = Max
ICCL    Power Supply Current             4.7  mA     (1),  Vcc = Max

(1) ICCL is measured with all inputs of one gate open and remaining
    inputs grounded.

AC CHARACTERISTICS

Symbol  Parameter        CL     Min  Typ  Max  Units
------  ---------------  -----  ---  ---  ---  -----
tPLH    Propagation Dly  15 pF  1.5  3.6  4.8  ns
tPLH    Propagation Dly  50 pF  2.0   --  7.0  ns
tPHL    Propagation Dly  15 pF  1.5  2.8  3.8  ns
tPHL    Propagation Dly  50 pF  2.0   --  5.5  ns

Data sheet transcription as plain text

VERILOG MODEL

// ============================================================================
// f64.v — 54F/74F64 4-2-3-2-Input AND-OR-Invert Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F64.txt (1980 Fairchild FAST Data Book, page 4-11)
//         (data sheet page marked "Preliminary")
//
// Logic function: Z = ~((A & B & C & D) | (E & F) | (G & H & I) | (J & K))
// Four AND groups of 4, 2, 3 and 2 inputs respectively are OR-ed and
// inverted: Z is LOW when any AND group has all of its inputs HIGH.
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   any input to Z   tPLH 2.0 / 7.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f64 (
    input  wire a, b, c, d, // 4-input AND group
    input  wire e, f,       // 2-input AND group
    input  wire g, h, i,    // 3-input AND group
    input  wire j, k,       // 2-input AND group
    output wire z           // output
);

    assign z = ~((a & b & c & d) | (e & f) | (g & h & i) | (j & k));

    specify
        // Propagation delay, any input to Z (data sheet: tPLH 1.5/3.6/4.8,
        // tPHL 1.5/2.8/3.8 ns)
        specparam tlh = 1.5:3.6:4.8;
        specparam thl = 1.5:2.8:3.8;

        (a, b, c, d, e, f, g, h, i, j, k => z) = (tlh, thl);
    endspecify

endmodule

f64.v as plain text