======================================================================== 74F10 TRIPLE 3-INPUT NAND GATE ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, page 4-7 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 74F10 contains three independent 3-input NAND gates in a 14-pin package. Logic function (each gate): Z = /(A * B * C) (output LOW only when all three inputs are HIGH) CONNECTION DIAGRAM (14-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------- --- ------------------- 1 A1 gate 1 input 14 Vcc 2 B1 gate 1 input 13 C1 gate 1 input 3 A2 gate 2 input 12 Z1 gate 1 output 4 B2 gate 2 input 11 C3 gate 3 input 5 C2 gate 2 input 10 B3 gate 3 input 6 Z2 gate 2 output 9 A3 gate 3 input 7 GND 8 Z3 gate 3 output TRUTH TABLE (each gate) ----------------------- A B C Z --- --- --- --- L X X H X L X H X X L H H H H L H = HIGH voltage level; L = LOW voltage level; X = don't care. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ----------- ------------- ------------- Inputs 0.5 / 0.375 Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- ---- ----- --------------------- ICCH Power Supply Current 2.1 mA VIN = Gnd, Vcc = Max ICCL Power Supply Current 7.7 mA VIN = Open, Vcc = Max AC CHARACTERISTICS ------------------ Symbol Parameter CL Min Typ Max Units ------ --------------- ----- --- --- --- ----- tPLH Propagation Dly 15 pF 1.5 2.9 3.9 ns tPLH Propagation Dly 50 pF 2.0 -- 6.0 ns tPHL Propagation Dly 15 pF 1.5 2.7 3.7 ns tPHL Propagation Dly 50 pF 2.0 -- 5.5 ns