======================================================================== 74F157 QUAD 2-INPUT MULTIPLEXER ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-22 ... 4-24 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F157 is a high speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four buffered outputs present the selected data in the true (non-inverted) form. The 'F157 can also be used to generate any four of the 16 different functions to two variables. The inverting counterpart is the 'F158. FUNCTIONAL DESCRIPTION ---------------------- The 'F157 selects four bits of data from two sources under the control of a common Select input (S). The Enable input (/E) is ACTIVE LOW. When /E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The 'F157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. Za = /E * ( I1a*S + I0a*/S ) Zb = /E * ( I1b*S + I0b*/S ) Zc = /E * ( I1c*S + I0c*/S ) Zd = /E * ( I1d*S + I0d*/S ) A common use of the 'F157 is the moving of data from two groups of registers to four common output busses; the particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a function generator -- the 'F157 can generate any four of the 16 different functions of two variables with one variable common, which is useful for implementing highly irregular logic. CONNECTION DIAGRAM (16-pin DIP) ------------------------------- Pin Function Pin Function --- -------------------- --- ------------------------------ 1 S Select input 16 Vcc 2 I0a Source 0, bit a 15 /E Enable input (active LOW) 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 Za Output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 Zc Output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 Zb Output b 10 I1d Source 1, bit d 8 GND 9 Zd Output d TRUTH TABLE (each section) -------------------------- /E S I0 I1 Z -- -- -- -- - H X X X L L H X L L L H X H H L L L X L L L H X H H = HIGH voltage level; L = LOW voltage level; X = immaterial. Summary: S = LOW selects the I0 (source 0) inputs; S = HIGH selects the I1 (source 1) inputs. The table applies to each of the four sections a, b, c, d: read I0 as I0a ... I0d, I1 as I1a ... I1d and Z as Za ... Zd. S and /E are common to all four sections. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ----------- ------------------------- ------------- I0a - I0d Source 0 Data Inputs 0.5 / 0.375 I1a - I1d Source 1 Data Inputs 0.5 / 0.375 /E Enable Input (Active LOW) 0.5 / 0.375 S Select Input 0.5 / 0.375 Za - Zd Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Test conditions: Vcc = Max, All Inputs = 4.5 V Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICC Power Supply Current 14 23 mA AC CHARACTERISTICS ------------------ Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay S to Zn 4.0 8.5 13 ns tPHL Propagation Delay S to Zn 3.0 6.0 9.0 ns tPLH Propagation Delay /E to Zn 2.0 6.5 8.0 ns tPHL Propagation Delay /E to Zn 2.0 4.5 7.0 ns tPLH Propagation Delay In to Zn 2.0 4.5 6.0 ns tPHL Propagation Delay In to Zn 2.0 3.5 4.5 ns