======================================================================== 74F545 OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1985 Fairchild FAST Data Book, pages 4-416 ... 4-418. The 1980 data book carries the 'F545 in its Section 3 selection guide only (page 3-29, description and logic symbol). Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F545 is an 8-bit, 3-state, high-speed transceiver. It provides bidirectional drive for bus-oriented microprocessor and digital communications systems. Straight through bidirectional transceivers are featured, with 20 mA bus drive capability on the A ports and 64 mA bus drive capability on the B ports. One input, Transmit/Receive (T//R) determines the direction of logic signals through the bidirectional transceiver. Transmit enables data from A ports to B ports; Receive enables data from B ports to A ports. The Output Enable input disables both A and B ports by placing them in a 3-state condition. o Higher Drive than 8304 o 8-Bit Bidirectional Data Flow Reduces System Package Count o 3-State Inputs/Outputs for Interfacing with Bus-Oriented Systems o 20 mA and 64 mA Bus Drive Capability on A and B Ports, Respectively o Transmit/Receive and Output Enable Simplify Control Logic CONNECTION DIAGRAM (20-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------------ --- ------------------------ 1 A0 Bus A, bit 0 20 Vcc 2 A1 Bus A, bit 1 19 B0 Bus B, bit 0 3 A2 Bus A, bit 2 18 B1 Bus B, bit 1 4 A3 Bus A, bit 3 17 B2 Bus B, bit 2 5 A4 Bus A, bit 4 16 B3 Bus B, bit 3 6 A5 Bus A, bit 5 15 B4 Bus B, bit 4 7 A6 Bus A, bit 6 14 B5 Bus B, bit 5 8 A7 Bus A, bit 7 13 B6 Bus B, bit 6 9 /OE Output Enable 12 B7 Bus B, bit 7 10 GND 11 T//R Transmit/Receive Each of the eight channels contains a back-to-back pair of non-inverting 3-state buffers; T//R selects which of the pair is enabled, and /OE gates both. TRUTH TABLE ----------- Inputs ------------ /OE T//R Outputs --- ---- ------------------ L L Bus B Data to Bus A L H Bus A Data to Bus B H X High Z H = HIGH voltage level; L = LOW voltage level; X = immaterial; Z = high impedance. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------- -------------------------------- ------------- /OE Output Enable Input (Active LOW) 0.5 / 0.75 T//R Transmit/Receive Input 0.5 / 0.75 A0 - A7 Side A 3-State Inputs or 1.75 / 0.406 3-State Outputs 75 / 15 B0 - B7 Side B 3-State Inputs or 1.75 / 0.406 3-State Outputs 75 / 40 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICCH Power Supply Current 70 90 mA Vcc = Max ICCL Power Supply Current 95 120 mA Vcc = Max ICCZ Power Supply Current 85 110 mA Vcc = Max AC CHARACTERISTICS ------------------ TA = +25 C 74F Vcc = +5.0V TA/Vcc = Com Symbol Parameter CL Min Typ Max Min Max Units ------ ----------------------------- ----- --- --- --- --- --- ----- tPLH Prop Delay An to Bn or Bn to 50 pF 2.5 4.2 6.0 2.5 7.0 ns An tPHL Prop Delay An to Bn or Bn to 50 pF 2.5 4.6 6.0 2.5 7.0 ns An tPZH Output Enable Time 50 pF 3.0 5.3 7.0 3.0 8.0 ns tPZL Output Enable Time 50 pF 3.5 6.0 8.0 3.5 9.0 ns tPHZ Output Disable Time 50 pF 3.0 5.0 6.5 3.0 7.5 ns tPLZ Output Disable Time 50 pF 2.0 5.0 6.5 2.0 7.5 ns