======================================================================== 74F74 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1980 Fairchild FAST Data Book, pages 4-12 ... 4-13 Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 'F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, /Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. CONNECTION DIAGRAM (14-pin DIP) ------------------------------- CP is active on the rising edge of the clock. Pin Function Pin Function --- ---------------------------- --- ---------------------------- 1 /CD1 Direct Clear 1 14 Vcc 2 D1 Data input 1 13 /CD2 Direct Clear 2 3 CP1 Clock Pulse 1 12 D2 Data input 2 4 /SD1 Direct Set 1 11 CP2 Clock Pulse 2 5 Q1 Output 1 10 /SD2 Direct Set 2 6 /Q1 Complementary output 1 9 Q2 Output 2 7 GND 8 /Q2 Complementary output 2 TRUTH TABLE (each half) ----------------------- Input Outputs D (@ tn) Q (@ tn+1) /Q (@ tn+1) -------- ---------- ----------- L L H H H L tn = bit time before the clock pulse; tn+1 = bit time after the clock pulse. H = HIGH voltage level; L = LOW voltage level. Asynchronous inputs: a LOW input to /SD sets Q to the HIGH level, and a LOW input to /CD sets Q to the LOW level. Clear and Set are independent of the clock. A simultaneous LOW on /CD and /SD makes both Q and /Q HIGH. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ---------------- --------------------------------------- ------------- D1, D2 Data Inputs 0.5 / 0.375 CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 0.5 / 0.375 /CD1, /CD2 Direct Clear Inputs (Active LOW) 0.5 / 1.125 /SD1, /SD2 Direct Set Inputs (Active LOW) 0.5 / 1.125 Q1, /Q1, Q2, /Q2 Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- ---- --- ----- -------------------- ICC Power Supply Current 10.5 16 mA Vcc = Max, VCP = 0 V AC CHARACTERISTICS ------------------ Clock parameters: Symbol Parameter Min Typ Max Units ------ --------------------------- --- --- --- ----- fmax Maximum Clock Frequency 100 125 -- MHz tPLH Prop Delay CPn to Qn or /Qn 2.0 4.4 6.0 ns tPHL Prop Delay CPn to Qn or /Qn 2.0 5.2 7.0 ns Asynchronous parameters -- propagation delay /CDn or /SDn to Qn or /Qn. Symbol Condition Min Typ Max Units ------ ------------ --- --- --- ----- tPLH VCP >= 2.0 V 2.0 3.6 5.5 ns tPHL VCP >= 2.0 V 2.0 6.5 8.0 ns tPLH VCP <= 0.8 V -- 2.8 -- ns tPHL VCP <= 0.8 V -- 5.5 -- ns AC OPERATING REQUIREMENTS ------------------------- Symbol Parameter Min Typ Max Units ------ ----------------------------------- --- --- --- ----- ts (H) Setup Time, HIGH -- Dn to CPn 2.0 -- -- ns ts (L) Setup Time, LOW -- Dn to CPn 3.0 -- -- ns th (H) Hold Time, HIGH -- Dn to CPn 1.0 -- -- ns th (L) Hold Time, LOW -- Dn to CPn 1.0 -- -- ns tw (H) CPn Pulse Width, HIGH 4.0 -- -- ns tw (L) CPn Pulse Width, LOW 5.0 -- -- ns tw (L) /CDn or /SDn Pulse Width LOW 4.0 -- -- ns trec Recovery Time -- /CDn or /SDn to CP 2.0 -- -- ns