======================================================================== 74F86 QUAD 2-INPUT EXCLUSIVE-OR GATE ======================================================================== Family: Fairchild FAST (Advanced Schottky TTL) Source: 1985 Fairchild FAST Data Book, page 4-30. The 1980 data book carries the 'F86 in its Section 3 gate selection guide only (page 3-4, connection diagram without specifications). Status: Released data sheet Ratings: Vcc = +5.0 V +/-5%, TA = 0 to +70 deg C DESCRIPTION ----------- The 74F86 contains four independent 2-input Exclusive-OR gates in a 14-pin package. Logic function (each gate): Z = A xor B CONNECTION DIAGRAM (14-pin DIP) ------------------------------- Pin Function Pin Function --- ------------------- --- ------------------- 1 A1 gate 1 input 14 Vcc 2 B1 gate 1 input 13 B4 gate 4 input 3 Z1 gate 1 output 12 A4 gate 4 input 4 A2 gate 2 input 11 Z4 gate 4 output 5 B2 gate 2 input 10 B3 gate 3 input 6 Z2 gate 2 output 9 A3 gate 3 input 7 GND 8 Z3 gate 3 output TRUTH TABLE (each gate) ----------------------- A B Z --- --- --- L L L L H H H L H H H L H = HIGH voltage level; L = LOW voltage level. INPUT LOADING / FAN-OUT ----------------------- Pin Names Description U.L. HIGH/LOW ----------- ------------- ------------- Inputs 0.5 / 0.375 Outputs 25 / 12.5 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE --------------------------------------------------- Symbol Parameter Min Typ Max Units ------ -------------------- --- --- --- ----- ICCL Power Supply Current 18 28 mA ICCH Power Supply Current 12 18 mA Conditions: ICCL -- Inputs HIGH; ICCH -- One Input LOW, One Input HIGH. Vcc = Max. AC CHARACTERISTICS ------------------ Symbol Parameter CL Min Typ Max Units ------ ------------------------------------ ----- --- --- --- ----- tPLH Propagation Delay (Other Input LOW) 50 pF 3.0 4.0 5.5 ns tPHL Propagation Delay (Other Input LOW) 50 pF 3.0 4.2 5.5 ns tPLH Propagation Delay (Other Input HIGH) 50 pF 3.5 5.3 7.0 ns tPHL Propagation Delay (Other Input HIGH) 50 pF 3.0 4.7 6.5 ns