// ============================================================================
// f02.v — 54F/74F02 Quad 2-Input NOR Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F02.txt (1980 Fairchild FAST Data Book, page 4-4)
//
// Logic function (each gate): Z = ~(A | B)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
// The sheet's second row, C_L = 50 pF, gives min/max only:
//   A or B to Z   tPLH 2.5 / 7.0   tPHL 2.0 / 5.5 ns
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f02 (
    input  wire a1, b1,     // gate 1 inputs
    output wire z1,         // gate 1 output
    input  wire a2, b2,     // gate 2 inputs
    output wire z2,         // gate 2 output
    input  wire a3, b3,     // gate 3 inputs
    output wire z3,         // gate 3 output
    input  wire a4, b4,     // gate 4 inputs
    output wire z4          // gate 4 output
);

    assign z1 = ~(a1 | b1);
    assign z2 = ~(a2 | b2);
    assign z3 = ~(a3 | b3);
    assign z4 = ~(a4 | b4);

    specify
        // Propagation delay, A or B to Z (data sheet: tPLH 2.0/3.5/4.8,
        // tPHL 1.5/2.6/3.5 ns)
        specparam tlh = 2.0:3.5:4.8;
        specparam thl = 1.5:2.6:3.5;

        (a1, b1 => z1) = (tlh, thl);
        (a2, b2 => z2) = (tlh, thl);
        (a3, b3 => z3) = (tlh, thl);
        (a4, b4 => z4) = (tlh, thl);
    endspecify

endmodule