// ============================================================================
// f153.v — 54F/74F153 Dual 4-Input Multiplexer
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F153.txt (1980 Fairchild FAST Data Book,
//         pages 4-19 ... 4-21)
//
// Two 4-input multiplexers with COMMON Select inputs (S0, S1) and
// individual active-LOW Enables (ea_n, eb_n). The outputs present data in
// the true (non-inverted) form. When an Enable is HIGH, the corresponding
// output is forced LOW regardless of all other inputs.
//
//   za = ~ea_n & (selected I_na)
//   zb = ~eb_n & (selected I_nb)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f153 (
    input  wire i0a, i1a, i2a, i3a,   // side A data inputs 0-3
    input  wire i0b, i1b, i2b, i3b,   // side B data inputs 0-3
    input  wire s0, s1,               // common select inputs
    input  wire ea_n,                 // side A enable (active LOW)
    input  wire eb_n,                 // side B enable (active LOW)
    output wire za,                   // side A output
    output wire zb                    // side B output
);

    // Selected data inputs (internal nodes)
    wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a);
    wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b);

    assign za = ~ea_n & da;
    assign zb = ~eb_n & db;

    specify
        // Propagation delay S_n to Z_n (data sheet: 3.0/9.5/13,
        // 3.0/8.0/10 ns)
        specparam tlh_s_z = 3.0:9.5:13;
        specparam thl_s_z = 3.0:8.0:10;

        // Propagation delay E_n to Z_n (data sheet: 3.0/8.0/12,
        // 3.0/7.5/12 ns)
        specparam tlh_e_z = 3.0:8.0:12;
        specparam thl_e_z = 3.0:7.5:12;

        // Propagation delay I_n to Z_n (data sheet: 2.0/5.0/8.0,
        // 2.0/4.5/6.5 ns)
        specparam tlh_i_z = 2.0:5.0:8.0;
        specparam thl_i_z = 2.0:4.5:6.5;

        (s0, s1 => za) = (tlh_s_z, thl_s_z);
        (s0, s1 => zb) = (tlh_s_z, thl_s_z);
        (ea_n => za)   = (tlh_e_z, thl_e_z);
        (eb_n => zb)   = (tlh_e_z, thl_e_z);
        (i0a, i1a, i2a, i3a => za) = (tlh_i_z, thl_i_z);
        (i0b, i1b, i2b, i3b => zb) = (tlh_i_z, thl_i_z);
    endspecify

endmodule