// ============================================================================
// f158.v — 54F/74F158 Quad 2-Input Multiplexer (Inverting)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F158.txt (1980 Fairchild FAST Data Book,
//         pages 4-25 ... 4-26) — PRELIMINARY data sheet
//
// Four 2-input multiplexers with a common Select input (S) and a common
// active-LOW Enable (e_n); pin-for-pin identical to the 'F157 except that
// the outputs are INVERTED. S LOW selects the I0 (source 0) inputs, S HIGH
// selects the I1 (source 1) inputs; the selected data appears inverted at
// Z_n. When e_n is HIGH, all outputs are forced HIGH regardless of all
// other inputs.
//
//   zn_n = e_n | ~(s ? i1n : i0n)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is
// preliminary: only TYPICAL values are given (min/max columns blank), so
// every specparam carries the typ value only.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f158 (
    input  wire s,                  // select input (common)
    input  wire e_n,                // enable input (active LOW)
    input  wire i0a, i1a,           // source 0/1 data inputs, bit a
    output wire za_n,               // inverted output a
    input  wire i0b, i1b,           // source 0/1 data inputs, bit b
    output wire zb_n,               // inverted output b
    input  wire i0c, i1c,           // source 0/1 data inputs, bit c
    output wire zc_n,               // inverted output c
    input  wire i0d, i1d,           // source 0/1 data inputs, bit d
    output wire zd_n                // inverted output d
);

    assign za_n = e_n | ~(s ? i1a : i0a);
    assign zb_n = e_n | ~(s ? i1b : i0b);
    assign zc_n = e_n | ~(s ? i1c : i0c);
    assign zd_n = e_n | ~(s ? i1d : i0d);

    specify
        // All values TYP only (preliminary data sheet; min/max columns
        // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF.

        // Propagation delay S to Z_n (data sheet: typ 6.3 / 6.2 ns)
        specparam tlh_s_z = 6.3;
        specparam thl_s_z = 6.2;

        // Propagation delay E_n to Z_n (data sheet: typ 4.6 / 4.5 ns)
        specparam tlh_e_z = 4.6;
        specparam thl_e_z = 4.5;

        // Propagation delay I_n to Z_n (data sheet: typ 2.9 / 2.8 ns)
        specparam tlh_i_z = 2.9;
        specparam thl_i_z = 2.8;

        (s => za_n) = (tlh_s_z, thl_s_z);
        (s => zb_n) = (tlh_s_z, thl_s_z);
        (s => zc_n) = (tlh_s_z, thl_s_z);
        (s => zd_n) = (tlh_s_z, thl_s_z);
        (e_n => za_n) = (tlh_e_z, thl_e_z);
        (e_n => zb_n) = (tlh_e_z, thl_e_z);
        (e_n => zc_n) = (tlh_e_z, thl_e_z);
        (e_n => zd_n) = (tlh_e_z, thl_e_z);
        (i0a, i1a => za_n) = (tlh_i_z, thl_i_z);
        (i0b, i1b => zb_n) = (tlh_i_z, thl_i_z);
        (i0c, i1c => zc_n) = (tlh_i_z, thl_i_z);
        (i0d, i1d => zd_n) = (tlh_i_z, thl_i_z);
    endspecify

endmodule