// ============================================================================
// f182.v — 54F/74F182 Carry Lookahead Generator
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F182.txt (1980 Fairchild FAST Data Book,
//         pages 4-41 ... 4-44)
//
// Accepts four pairs of active-LOW Carry Propagate (/P0-/P3) and Carry
// Generate (/G0-/G3) signals plus an active-HIGH Carry input (Cn), and
// provides three active-HIGH carries (Cn+x, Cn+y, Cn+z) together with
// active-LOW Carry Propagate (/P) and Carry Generate (/G) outputs.
//
// Logic equations (from data sheet, in terms of internal positive logic
// Pn = ~p_n[x], Gn = ~g_n[x]):
//   Cn+x = G0 + P0 * Cn
//   Cn+y = G1 + P1 * G0 + P1 * P0 * Cn
//   Cn+z = G2 + P2 * G1 + P2 * P1 * G0 + P2 * P1 * P0 * Cn
//   /G   = ~(G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * G0)
//   /P   = ~(P3 * P2 * P1 * P0)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F PRELIMINARY column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF),
// typical values only — Min/Max columns were left blank.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f182 (
    input  wire g1_n,      // Pin  1 — /G1   Carry Generate input 1 (active LOW)
    input  wire p1_n,      // Pin  2 — /P1   Carry Propagate input 1 (active LOW)
    input  wire g0_n,      // Pin  3 — /G0   Carry Generate input 0 (active LOW)
    input  wire p0_n,      // Pin  4 — /P0   Carry Propagate input 0 (active LOW)
    input  wire g3_n,      // Pin  5 — /G3   Carry Generate input 3 (active LOW)
    input  wire p3_n,      // Pin  6 — /P3   Carry Propagate input 3 (active LOW)
    output wire p_n,       // Pin  7 — /P    Carry Propagate output (active LOW)
    output wire cn_z,      // Pin  9 — Cn+z  Carry output z
    output wire g_n,       // Pin 10 — /G    Carry Generate output (active LOW)
    output wire cn_y,      // Pin 11 — Cn+y  Carry output y
    output wire cn_x,      // Pin 12 — Cn+x  Carry output x
    input  wire cn,        // Pin 13 — Cn    Carry input
    input  wire g2_n,      // Pin 14 — /G2   Carry Generate input 2 (active LOW)
    input  wire p2_n       // Pin 15 — /P2   Carry Propagate input 2 (active LOW)
);

    wire g0 = ~g0_n, g1 = ~g1_n, g2 = ~g2_n, g3 = ~g3_n;
    wire p0 = ~p0_n, p1 = ~p1_n, p2 = ~p2_n, p3 = ~p3_n;

    assign cn_x = g0 | (p0 & cn);
    assign cn_y = g1 | (p1 & g0) | (p1 & p0 & cn);
    assign cn_z = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cn);
    assign g_n  = ~(g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0));
    assign p_n  = ~(p3 & p2 & p1 & p0);

    specify
        // Propagation delays — typ values only (preliminary datasheet):
        //   Cn  to Cn+x/y/z:       tPLH 4.6, tPHL 4.5 ns
        //   Gn  to Cn+x/y/z:       tPLH 2.9, tPHL 2.8 ns  (G0–G2 only)
        //   Pn  to Cn+x/y/z:       tPLH 2.9, tPHL 2.8 ns  (P0–P2 only)
        //   Gn  to /G:             tPLH 4.5, tPHL 4.3 ns
        //   Pn  to /G:             tPLH 4.5, tPHL 4.3 ns  (P1–P3 only)
        //   Pn  to /P:             tPLH 5.0, tPHL 4.8 ns
        specparam cn_tlh  = 4.6, cn_thl  = 4.5;
        specparam gpn_tlh = 2.9, gpn_thl = 2.8;
        specparam g_tlh   = 4.5, g_thl   = 4.3;
        specparam p_tlh   = 5.0, p_thl   = 4.8;

        // Cn to carry outputs
        (cn => cn_x) = (cn_tlh, cn_thl);
        (cn => cn_y) = (cn_tlh, cn_thl);
        (cn => cn_z) = (cn_tlh, cn_thl);

        // /G0 /G1 /G2 /P0 /P1 /P2 to carry outputs
        (g0_n, p0_n => cn_x) = (gpn_tlh, gpn_thl);
        (g0_n, p0_n, g1_n, p1_n => cn_y) = (gpn_tlh, gpn_thl);
        (g0_n, p0_n, g1_n, p1_n, g2_n, p2_n => cn_z) = (gpn_tlh, gpn_thl);

        // /G inputs to /G output (all four)
        (g0_n, g1_n, g2_n, g3_n => g_n) = (g_tlh, g_thl);

        // /P1 /P2 /P3 to /G output
        (p1_n, p2_n, p3_n => g_n) = (g_tlh, g_thl);

        // /Pn to /P output (all four)
        (p0_n, p1_n, p2_n, p3_n => p_n) = (p_tlh, p_thl);
    endspecify

endmodule