// ============================================================================
// f240.v — 54F/74F240 Octal Buffer/Line Driver, Inverting (3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F240.txt (1980 Fairchild FAST Data Book,
//         pages 4-68 ... 4-69; shared data sheet with 'F241/'F244,
//         preliminary)
//
// Eight inverting 3-state buffers in two independently enabled groups of
// four. Group 1: 1D1..1D4 -> 1O1..1O4, enabled by OE1_n LOW.
// Group 2: 2D1..2D4 -> 2O1..2O4, enabled by OE2_n LOW.
//
// Truth table (each buffer): OE_n=L, D=L -> H;  OE_n=L, D=H -> L;
//                            OE_n=H, D=X -> Z.
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), in ns.
// The preliminary data sheet lists TYPICAL values only (Min/Max columns
// left blank), so the specparams below are typ-only single values.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f240 (
    input  wire oe1_n,                      // output enable, group 1 (active LOW)
    input  wire d1_1, d1_2, d1_3, d1_4,     // group 1 data inputs
    output wire o1_1, o1_2, o1_3, o1_4,     // group 1 outputs (inverting, 3-state)
    input  wire oe2_n,                      // output enable, group 2 (active LOW)
    input  wire d2_1, d2_2, d2_3, d2_4,     // group 2 data inputs
    output wire o2_1, o2_2, o2_3, o2_4      // group 2 outputs (inverting, 3-state)
);

    assign o1_1 = oe1_n ? 1'bz : ~d1_1;
    assign o1_2 = oe1_n ? 1'bz : ~d1_2;
    assign o1_3 = oe1_n ? 1'bz : ~d1_3;
    assign o1_4 = oe1_n ? 1'bz : ~d1_4;

    assign o2_1 = oe2_n ? 1'bz : ~d2_1;
    assign o2_2 = oe2_n ? 1'bz : ~d2_2;
    assign o2_3 = oe2_n ? 1'bz : ~d2_3;
    assign o2_4 = oe2_n ? 1'bz : ~d2_4;

    specify
        // Data sheet AC Characteristics (preliminary: typ values only,
        // min/max columns blank), C_L = 15 pF; disable times measured with
        // C_L = 5.0 pF, R_L = 90 ohm:
        //   tPLH = 4.5, tPHL = 4.5  (Propagation Delay Data to Output)
        //   tPZH = 6.0, tPZL = 10   (Output Enable Time)
        //   tPHZ = 10,  tPLZ = 6.0  (Output Disable Time)
        specparam tlh = 4.5;   // tPLH, data to output
        specparam thl = 4.5;   // tPHL, data to output
        specparam tlz = 6.0;   // tPLZ, output disable (0 -> Z)
        specparam tzh = 6.0;   // tPZH, output enable  (Z -> 1)
        specparam thz = 10.0;  // tPHZ, output disable (1 -> Z)
        specparam tzl = 10.0;  // tPZL, output enable  (Z -> 0)

        (d1_1, oe1_n => o1_1) = (tlh, thl, tlz, tzh, thz, tzl);
        (d1_2, oe1_n => o1_2) = (tlh, thl, tlz, tzh, thz, tzl);
        (d1_3, oe1_n => o1_3) = (tlh, thl, tlz, tzh, thz, tzl);
        (d1_4, oe1_n => o1_4) = (tlh, thl, tlz, tzh, thz, tzl);

        (d2_1, oe2_n => o2_1) = (tlh, thl, tlz, tzh, thz, tzl);
        (d2_2, oe2_n => o2_2) = (tlh, thl, tlz, tzh, thz, tzl);
        (d2_3, oe2_n => o2_3) = (tlh, thl, tlz, tzh, thz, tzl);
        (d2_4, oe2_n => o2_4) = (tlh, thl, tlz, tzh, thz, tzl);
    endspecify

endmodule