// ============================================================================
// f258.v — 54F/74F258 Quad 2-Input Multiplexer, Inverting
//          (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F258.txt (1980 Fairchild FAST Data Book,
//         pages 4-82 ... 4-84) — PRELIMINARY data sheet
//
// Four 2-input multiplexers with a common Data Select input S and a common
// active-LOW 3-state Output Enable (OE_n). When S is LOW the I0x inputs
// are selected, when HIGH the I1x inputs. Data appears at the outputs in
// INVERTED form. A HIGH on OE_n forces all outputs to the high impedance
// state.
//
//   Z_nx = OE_n ? HiZ : ~(S ? I1x : I0x)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is
// preliminary: only TYPICAL values are given for the data/select paths
// (min/max columns blank), so those specparams carry the typ value only.
// The Output Enable/Disable time rows (tPZH/tPZL/tPHZ/tPLZ) are printed
// entirely BLANK on this data sheet — no values exist to transcribe, so no
// OE_n specify path is given and the 3-state transitions propagate with
// zero delay. (No timing invented; noted in the testbench and report.)
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f258 (
    input  wire s,          // common data select input
    input  wire oe_n,       // 3-state output enable (active LOW)
    input  wire i0a, i1a,   // source 0/1 data inputs, bit a
    output wire za_n,       // inverting output a
    input  wire i0b, i1b,   // source 0/1 data inputs, bit b
    output wire zb_n,       // inverting output b
    input  wire i0c, i1c,   // source 0/1 data inputs, bit c
    output wire zc_n,       // inverting output c
    input  wire i0d, i1d,   // source 0/1 data inputs, bit d
    output wire zd_n        // inverting output d
);

    assign za_n = oe_n ? 1'bz : ~(s ? i1a : i0a);
    assign zb_n = oe_n ? 1'bz : ~(s ? i1b : i0b);
    assign zc_n = oe_n ? 1'bz : ~(s ? i1c : i0c);
    assign zd_n = oe_n ? 1'bz : ~(s ? i1d : i0d);

    specify
        // All values TYP only (preliminary data sheet; min/max columns
        // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF.

        // Propagation delay In to Z_n (data sheet: typ 2.9 / 2.8 ns)
        specparam tlh_i = 2.9;
        specparam thl_i = 2.8;

        // Propagation delay S to Z_n (data sheet: typ 6.3 / 6.2 ns)
        specparam tlh_s = 6.3;
        specparam thl_s = 6.2;

        (i0a, i1a => za_n) = (tlh_i, thl_i);
        (i0b, i1b => zb_n) = (tlh_i, thl_i);
        (i0c, i1c => zc_n) = (tlh_i, thl_i);
        (i0d, i1d => zd_n) = (tlh_i, thl_i);
        (s => za_n) = (tlh_s, thl_s);
        (s => zb_n) = (tlh_s, thl_s);
        (s => zc_n) = (tlh_s, thl_s);
        (s => zd_n) = (tlh_s, thl_s);

        // Output Enable/Disable times OE_n to Z_n (tPZH/tPZL/tPHZ/tPLZ):
        // rows printed BLANK on this preliminary data sheet, so no OE_n
        // path is specified — 3-state transitions propagate with zero
        // delay rather than with invented values.
    endspecify

endmodule