// ============================================================================
// f352.v — 54F/74F352 Dual 4-Input Multiplexer (Inverting)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F352.txt (1980 Fairchild FAST Data Book,
//         pages 4-94 ... 4-96) — PRELIMINARY data sheet
//
// Two 4-input multiplexers with COMMON Select inputs (S0, S1) and
// individual active-LOW Enables (ea_n, eb_n); the functional equivalent of
// the 'F153 except the outputs are INVERTED. When an Enable is HIGH, the
// corresponding output is forced HIGH regardless of all other inputs.
//
//   za_n = ea_n | ~(selected I_na)
//   zb_n = eb_n | ~(selected I_nb)
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is
// preliminary: only TYPICAL values are given (min/max columns blank), so
// every specparam carries the typ value only.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f352 (
    input  wire i0a, i1a, i2a, i3a,   // side A data inputs 0-3
    input  wire i0b, i1b, i2b, i3b,   // side B data inputs 0-3
    input  wire s0, s1,               // common select inputs
    input  wire ea_n,                 // side A enable (active LOW)
    input  wire eb_n,                 // side B enable (active LOW)
    output wire za_n,                 // side A inverted output
    output wire zb_n                  // side B inverted output
);

    // Selected data inputs (internal nodes)
    wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a);
    wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b);

    assign za_n = ea_n | ~da;
    assign zb_n = eb_n | ~db;

    specify
        // All values TYP only (preliminary data sheet; min/max columns
        // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF.

        // Propagation delay S_n to Z_n (data sheet: typ 6.3 / 6.2 ns)
        specparam tlh_s_z = 6.3;
        specparam thl_s_z = 6.2;

        // Propagation delay E_n to Z_n (data sheet: typ 4.6 / 4.5 ns)
        specparam tlh_e_z = 4.6;
        specparam thl_e_z = 4.5;

        // Propagation delay I_n to Z_n (data sheet: typ 2.9 / 2.8 ns)
        specparam tlh_i_z = 2.9;
        specparam thl_i_z = 2.8;

        (s0, s1 => za_n) = (tlh_s_z, thl_s_z);
        (s0, s1 => zb_n) = (tlh_s_z, thl_s_z);
        (ea_n => za_n)   = (tlh_e_z, thl_e_z);
        (eb_n => zb_n)   = (tlh_e_z, thl_e_z);
        (i0a, i1a, i2a, i3a => za_n) = (tlh_i_z, thl_i_z);
        (i0b, i1b, i2b, i3b => zb_n) = (tlh_i_z, thl_i_z);
    endspecify

endmodule