// ============================================================================
// f534.v — 54F/74F534 Octal D-Type Flip-Flop, Inverting
//          (With 3-State Outputs)
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F534.txt (1980 Fairchild FAST Data Book,
//         pages 4-110 ... 4-111) — PRELIMINARY data sheet.
//
// Eight edge-triggered D-type flip-flops with inverting 3-state outputs:
// the same as the 'F374 except the outputs are inverted. The flip-flops
// store the state of their D inputs on the LOW-to-HIGH Clock (CP)
// transition. Output Enable (OE_n) LOW drives the outputs; OE_n HIGH
// forces the high-impedance state without affecting the flip-flops.
//
// Note: the printed functional description on page 4-111 was copied from
// the 'F374 and still says "3-state true outputs"; the device title,
// connection diagram, pin table and header description all confirm the
// outputs are inverted (O_0-bar ... O_7-bar), which is what is modeled.
//
// Timing values from the data sheet AC Characteristics table
// (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The preliminary sheet gives
// TYP ONLY (min/max columns blank). The f_max row was printed with no
// values; not modeled.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays. The complementary
// outputs O_n-bar are named o0_n ... o7_n (cf. q_n in f74).
// ============================================================================
`timescale 1ns/100ps

module f534 (
    input  wire oe_n,                           // 3-state output enable
                                                //   (active LOW)
    input  wire cp,                             // clock pulse (active rising
                                                //   edge)
    input  wire d0, d1, d2, d3,                 // data inputs 0-3
    input  wire d4, d5, d6, d7,                 // data inputs 4-7
    output wire o0_n, o1_n, o2_n, o3_n,         // complementary 3-state
    output wire o4_n, o5_n, o6_n, o7_n          //   outputs 0-7
);

    // Edge-triggered flip-flop bank: D stored on the rising CP edge.
    reg [7:0] q_int;

    always @(posedge cp) begin
        q_int <= {d7, d6, d5, d4, d3, d2, d1, d0};
    end

    // Inverting 3-state output buffers (OE_n HIGH -> high impedance)
    assign o0_n = oe_n ? 1'bz : ~q_int[0];
    assign o1_n = oe_n ? 1'bz : ~q_int[1];
    assign o2_n = oe_n ? 1'bz : ~q_int[2];
    assign o3_n = oe_n ? 1'bz : ~q_int[3];
    assign o4_n = oe_n ? 1'bz : ~q_int[4];
    assign o5_n = oe_n ? 1'bz : ~q_int[5];
    assign o6_n = oe_n ? 1'bz : ~q_int[6];
    assign o7_n = oe_n ? 1'bz : ~q_int[7];

    specify
        // Propagation delay CP to O_n (data sheet, TYP ONLY — preliminary
        // sheet, min/max blank: tPLH 5.5, tPHL 5.5 ns)
        specparam tlh_cp_o = 5.5;
        specparam thl_cp_o = 5.5;

        // Output enable/disable time OE_n to O_n (data sheet, TYP ONLY:
        // tPZH 6.5, tPZL 6.5, tPHZ 5.5, tPLZ 4.5 ns; disable times
        // measured with C_L = 5 pF)
        specparam tzh_oe_o = 6.5;
        specparam tzl_oe_o = 6.5;
        specparam thz_oe_o = 5.5;
        specparam tlz_oe_o = 4.5;

        // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0):
        // CP causes only 0->1/1->0 transitions, OE_n only Z transitions.
        (oe_n, cp => o0_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o1_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o2_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o3_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o4_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o5_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o6_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);
        (oe_n, cp => o7_n) = (tlh_cp_o, thl_cp_o, tlz_oe_o, tzh_oe_o, thz_oe_o, tzl_oe_o);

        // AC operating requirements (data sheet, +25 C 5.0 V minima):
        // ts(H) 2.0, ts(L) 2.0, th(H) 2.0, th(L) 2.0, tw(H) CP 7.0,
        // tw(L) CP 6.0 ns. Icarus Verilog does not support timing checks;
        // kept (guarded) for simulators that do.
`ifndef __ICARUS__
        specparam ts_h = 2.0;
        specparam ts_l = 2.0;
        specparam th_h = 2.0;
        specparam th_l = 2.0;
        specparam tw_cp_h = 7.0;
        specparam tw_cp_l = 6.0;

        $setup(d0, posedge cp, ts_h);
        $setup(d1, posedge cp, ts_h);
        $setup(d2, posedge cp, ts_h);
        $setup(d3, posedge cp, ts_h);
        $setup(d4, posedge cp, ts_h);
        $setup(d5, posedge cp, ts_h);
        $setup(d6, posedge cp, ts_h);
        $setup(d7, posedge cp, ts_h);
        $hold(posedge cp, d0, th_h);
        $hold(posedge cp, d1, th_h);
        $hold(posedge cp, d2, th_h);
        $hold(posedge cp, d3, th_h);
        $hold(posedge cp, d4, th_h);
        $hold(posedge cp, d5, th_h);
        $hold(posedge cp, d6, th_h);
        $hold(posedge cp, d7, th_h);
        $width(posedge cp, tw_cp_h);
        $width(negedge cp, tw_cp_l);
`endif
    endspecify

endmodule