// ============================================================================
// f86.v — 54F/74F86 Quad 2-Input Exclusive-OR Gate
//
// Fairchild FAST (Advanced Schottky TTL)
// Source: docs/devices/54F74F86.txt (1985 Fairchild FAST Data Book,
//         page 4-30 — the 1980 data book covers the 'F86 in its Section 3
//         gate selection guide only).
//
// Logic function (each gate): Z = A ^ B
//
// Timing values from the data sheet AC Characteristics table,
// 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 50 pF), min:typ:max ns.
// The data sheet specifies each gate twice, once with the other input LOW
// and once with it HIGH, so the paths are state dependent: with the other
// input LOW the gate passes its input, with it HIGH the gate inverts.
//
// Ports are scalar and named after the data sheet pin names: Icarus Verilog
// does not fully support multi-bit (parallel) specify path connections, so
// vector ports would get incorrect per-bit delays.
// ============================================================================
`timescale 1ns/100ps

module f86 (
    input  wire a1, b1,     // gate 1 inputs
    output wire z1,         // gate 1 output
    input  wire a2, b2,     // gate 2 inputs
    output wire z2,         // gate 2 output
    input  wire a3, b3,     // gate 3 inputs
    output wire z3,         // gate 3 output
    input  wire a4, b4,     // gate 4 inputs
    output wire z4          // gate 4 output
);

    assign z1 = a1 ^ b1;
    assign z2 = a2 ^ b2;
    assign z3 = a3 ^ b3;
    assign z4 = a4 ^ b4;

    specify
        // Propagation delay, other input LOW (data sheet: tPLH 3.0/4.0/5.5,
        // tPHL 3.0/4.2/5.5 ns)
        specparam tlh_lo = 3.0:4.0:5.5;
        specparam thl_lo = 3.0:4.2:5.5;

        // Propagation delay, other input HIGH (data sheet: tPLH 3.5/5.3/7.0,
        // tPHL 3.0/4.7/6.5 ns)
        specparam tlh_hi = 3.5:5.3:7.0;
        specparam thl_hi = 3.0:4.7:6.5;

        if (b1 == 1'b0) (a1 => z1) = (tlh_lo, thl_lo);
        if (b1 == 1'b1) (a1 => z1) = (tlh_hi, thl_hi);
        if (a1 == 1'b0) (b1 => z1) = (tlh_lo, thl_lo);
        if (a1 == 1'b1) (b1 => z1) = (tlh_hi, thl_hi);

        if (b2 == 1'b0) (a2 => z2) = (tlh_lo, thl_lo);
        if (b2 == 1'b1) (a2 => z2) = (tlh_hi, thl_hi);
        if (a2 == 1'b0) (b2 => z2) = (tlh_lo, thl_lo);
        if (a2 == 1'b1) (b2 => z2) = (tlh_hi, thl_hi);

        if (b3 == 1'b0) (a3 => z3) = (tlh_lo, thl_lo);
        if (b3 == 1'b1) (a3 => z3) = (tlh_hi, thl_hi);
        if (a3 == 1'b0) (b3 => z3) = (tlh_lo, thl_lo);
        if (a3 == 1'b1) (b3 => z3) = (tlh_hi, thl_hi);

        if (b4 == 1'b0) (a4 => z4) = (tlh_lo, thl_lo);
        if (b4 == 1'b1) (a4 => z4) = (tlh_hi, thl_hi);
        if (a4 == 1'b0) (b4 => z4) = (tlh_lo, thl_lo);
        if (a4 == 1'b1) (b4 => z4) = (tlh_hi, thl_hi);
    endspecify

endmodule