DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each half) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually exclusive active LOW outputs. Each decoder has an active LOW Enable input which can be used as a data input for a 4-output demultiplexer. Each half of the 'F139 can be used as a function generator providing all four minterms of two variables. o Multifunction Capability o Two Completely Independent 1-of-4 Decoders o Active LOW Mutually Exclusive Outputs
The 'F139 is a high-speed dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each of which accepts two binary weighted inputs (A0-A1) and provides four mutually exclusive active LOW outputs (/O0-/O3). Each decoder has an active LOW enable (/E). When /E is HIGH all outputs are forced HIGH. The enable can be used as the data input for a 4-output demultiplexer application. Each half of the 'F139 generates all four minterms of two variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in Figure a, and thereby reducing the number of packages required in a logic network.
Pin Function Pin Function --- ---------------------- --- ---------------------- 1 /Ea Enable a 16 Vcc 2 A0a Address a bit 0 15 /Eb Enable b 3 A1a Address a bit 1 14 A0b Address b bit 0 4 /O0a Output a 0 13 A1b Address b bit 1 5 /O1a Output a 1 12 /O0b Output b 0 6 /O2a Output a 2 11 /O1b Output b 1 7 /O3a Output a 3 10 /O2b Output b 2 8 GND 9 /O3b Output b 3 The "a" and "b" suffixes distinguish the two independent decoders; each has its own Enable, address and output pins, and they share only Vcc and GND.
Inputs Outputs ------------- ---------------- /E A0 A1 /O0 /O1 /O2 /O3 --- --- --- --- --- --- --- H X X H H H H L L L L H H H L H L H L H H L L H H H L H L H H H H H L H = HIGH voltage level; L = LOW voltage level; X = immaterial.
Pin Names Description U.L. HIGH/LOW ---------- -------------------------- ------------- A0, A1 Address Inputs 0.5 / 0.375 /E Enable Inputs (Active LOW) 0.5 / 0.375 /O0 - /O3 Outputs (Active LOW) 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------- ICC Power Supply Current 13 20 mA Vcc = Max
TA = +25 C 74F
Vcc = +5.0V TA/Vcc = Com
Symbol Parameter CL Min Typ Max Min Max Units
------ ----------------------------- ----- --- --- --- --- --- -----
tPLH Prop Delay A0 or A1 to /On 50 pF 3.5 5.3 7.5 3.0 8.5 ns
tPHL Prop Delay A0 or A1 to /On 50 pF 4.0 6.1 8.0 4.0 9.0 ns
tPLH Prop Delay /E to /On 50 pF 3.5 5.4 7.0 3.5 8.0 ns
tPHL Prop Delay /E to /On 50 pF 3.0 4.7 6.5 3.0 7.5 ns
Data sheet transcription as plain text
// ============================================================================ // f139.v — 54F/74F139 Dual 1-of-4 Decoder/Demultiplexer // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F139.txt (1985 Fairchild FAST Data Book, // pages 4-49 ... 4-52 — the 1980 data book carries the 'F139 in // its Section 3 selection guide only, page 3-15). // // Two completely independent 1-of-4 decoders, each accepting two binary // weighted address inputs (A0, A1) and providing four mutually exclusive // active LOW outputs (/O0 - /O3). Each decoder has its own active LOW // Enable (/E); when /E is HIGH all four of that decoder's outputs are // forced HIGH. The Enable can be used as the data input of a 4-output // demultiplexer. Each half generates all four minterms of two variables. // // /On = ~(~/E & ({a1, a0} == n)) // // The "a" and "b" suffixes distinguish the two decoders; they share only // V_CC and GND. // // Timing values from the data sheet AC Characteristics table, T_A = +25 C, // V_CC = +5.0 V, C_L = 50 pF column, min:typ:max ns. The sheet's second // column, 74F over the commercial T_A/V_CC range, gives min/max only: // // A0 or A1 to /On tPLH 3.0 / 8.5 tPHL 4.0 / 9.0 ns // /E to /On tPLH 3.5 / 8.0 tPHL 3.0 / 7.5 ns // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f139 ( input wire e_na, // half a enable (active LOW) input wire a0a, a1a, // half a address inputs output wire o0a_n, o1a_n, o2a_n, o3a_n, // half a outputs (active LOW) input wire e_nb, // half b enable (active LOW) input wire a0b, a1b, // half b address inputs output wire o0b_n, o1b_n, o2b_n, o3b_n // half b outputs (active LOW) ); // Internal enable terms: each half's outputs are all HIGH unless that // half's /E is LOW. wire ea = ~e_na; wire eb = ~e_nb; assign o0a_n = ~(ea & ~a1a & ~a0a); assign o1a_n = ~(ea & ~a1a & a0a); assign o2a_n = ~(ea & a1a & ~a0a); assign o3a_n = ~(ea & a1a & a0a); assign o0b_n = ~(eb & ~a1b & ~a0b); assign o1b_n = ~(eb & ~a1b & a0b); assign o2b_n = ~(eb & a1b & ~a0b); assign o3b_n = ~(eb & a1b & a0b); specify // T_A = +25 C, V_CC = +5.0 V, C_L = 50 pF, min:typ:max ns. // Propagation delay A0 or A1 to /On // (data sheet: tPLH 3.5/5.3/7.5, tPHL 4.0/6.1/8.0) specparam tlh_a = 3.5:5.3:7.5; specparam thl_a = 4.0:6.1:8.0; // Propagation delay /E to /On // (data sheet: tPLH 3.5/5.4/7.0, tPHL 3.0/4.7/6.5) specparam tlh_e = 3.5:5.4:7.0; specparam thl_e = 3.0:4.7:6.5; (a0a, a1a => o0a_n) = (tlh_a, thl_a); (a0a, a1a => o1a_n) = (tlh_a, thl_a); (a0a, a1a => o2a_n) = (tlh_a, thl_a); (a0a, a1a => o3a_n) = (tlh_a, thl_a); (e_na => o0a_n) = (tlh_e, thl_e); (e_na => o1a_n) = (tlh_e, thl_e); (e_na => o2a_n) = (tlh_e, thl_e); (e_na => o3a_n) = (tlh_e, thl_e); (a0b, a1b => o0b_n) = (tlh_a, thl_a); (a0b, a1b => o1b_n) = (tlh_a, thl_a); (a0b, a1b => o2b_n) = (tlh_a, thl_a); (a0b, a1b => o3b_n) = (tlh_a, thl_a); (e_nb => o0b_n) = (tlh_e, thl_e); (e_nb => o1b_n) = (tlh_e, thl_e); (e_nb => o2b_n) = (tlh_e, thl_e); (e_nb => o3b_n) = (tlh_e, thl_e); endspecify endmodule