DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F151 is a high speed 8-input digital multiplexer. It provides in one package, the ability to select one line of data from up to eight sources. The 'F151 can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.
The 'F151 is a logical implementation of a single pole, 8-position
switch with the switch position controlled by the state of three Select
inputs, S0, S1, S2. Both assertion and negation outputs are provided.
The Enable input (/E) is active LOW. When it is not activated, the
negation output is HIGH and the assertion output is LOW regardless of
all other inputs.
The logic function provided at the output is:
Z = /E * ( I0*/S0*/S1*/S2 + I1*S0*/S1*/S2 + I2*/S0*S1*/S2
+ I3*S0*S1*/S2 + I4*/S0*/S1*S2 + I5*S0*/S1*S2
+ I6*/S0*S1*S2 + I7*S0*S1*S2 )
The 'F151 provides the ability, in one package, to select from eight
sources of data or control information. By proper manipulation of the
inputs, the 'F151 can provide any logic function of four variables and
its negation.
Pin Function Pin Function --- ------------------------------ --- ------------------- 1 I3 Data input 3 16 Vcc 2 I2 Data input 2 15 I4 Data input 4 3 I1 Data input 1 14 I5 Data input 5 4 I0 Data input 0 13 I6 Data input 6 5 Z Data output 12 I7 Data input 7 6 /Z Inverted data output 11 S0 Select input 0 7 /E Enable input (active LOW) 10 S1 Select input 1 8 GND 9 S2 Select input 2
/E S2 S1 S0 /Z Z -- -- -- -- --- --- H X X X H L L L L L /I0 I0 L L L H /I1 I1 L L H L /I2 I2 L L H H /I3 I3 L H L L /I4 I4 L H L H /I5 I5 L H H L /I6 I6 L H H H /I7 I7 H = HIGH Voltage Level; L = LOW Voltage Level; X = don't care. /I0 ... /I7 denote the complement of the corresponding data input.
Pin Names Description U.L. HIGH/LOW ----------- ------------------------- ------------- I0 - I7 Data Inputs 0.5 / 0.375 S0 - S2 Select Inputs 0.5 / 0.375 /E Enable Input (Active LOW) 0.5 / 0.375 Z Data Output 25 / 12.5 /Z Inverted Data Output 25 / 12.5
Symbol Parameter Min Typ Max Units Conditions ------ -------------------- --- --- --- ----- ---------------------- ICC Power Supply Current 11 mA Vcc = Max, VIN = 4.5 V
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay Sn to /Z -- 6.3 -- ns tPHL Propagation Delay Sn to /Z -- 6.2 -- ns tPLH Propagation Delay Sn to Z -- 8.1 -- ns tPHL Propagation Delay Sn to Z -- 7.9 -- ns tPLH Propagation Delay /E to /Z -- 4.6 -- ns tPHL Propagation Delay /E to /Z -- 4.5 -- ns tPLH Propagation Delay /E to Z -- 6.4 -- ns tPHL Propagation Delay /E to Z -- 6.2 -- ns tPLH Propagation Delay In to /Z -- 2.9 -- ns tPHL Propagation Delay In to /Z -- 2.8 -- ns tPLH Propagation Delay In to Z -- 4.7 -- ns tPHL Propagation Delay In to Z -- 4.5 -- ns
Data sheet transcription as plain text
// ============================================================================ // f151.v — 54F/74F151 8-Input Multiplexer // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F151.txt (1980 Fairchild FAST Data Book, // pages 4-16 ... 4-18) — PRELIMINARY data sheet // // Selects one of eight data inputs under control of the Select inputs // S0, S1, S2. Both assertion (Z) and negation (Z_n) outputs are provided. // The Enable input (e_n) is active LOW: when HIGH, Z is forced LOW and // Z_n is forced HIGH regardless of all other inputs. // // Z = ~e_n & (selected I_n) // Z_n = e_n | ~(selected I_n) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF). The sheet is // preliminary: only TYPICAL values are given (min/max columns blank), so // every specparam carries the typ value only. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f151 ( input wire i0, i1, i2, i3, // data inputs 0-3 input wire i4, i5, i6, i7, // data inputs 4-7 input wire s0, s1, s2, // select inputs input wire e_n, // enable input (active LOW) output wire z, // data output output wire z_n // inverted data output ); // Selected data input (internal node) wire d = s2 ? (s1 ? (s0 ? i7 : i6) : (s0 ? i5 : i4)) : (s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0)); assign z = ~e_n & d; assign z_n = e_n | ~d; specify // All values TYP only (preliminary data sheet; min/max columns // left blank), 54F/74F +25 C 5.0 V C_L = 15 pF. // Propagation delay S_n to Z_n (data sheet: typ 6.3 / 6.2 ns) specparam tlh_s_zn = 6.3; specparam thl_s_zn = 6.2; // Propagation delay S_n to Z (data sheet: typ 8.1 / 7.9 ns) specparam tlh_s_z = 8.1; specparam thl_s_z = 7.9; // Propagation delay E_n to Z_n (data sheet: typ 4.6 / 4.5 ns) specparam tlh_e_zn = 4.6; specparam thl_e_zn = 4.5; // Propagation delay E_n to Z (data sheet: typ 6.4 / 6.2 ns) specparam tlh_e_z = 6.4; specparam thl_e_z = 6.2; // Propagation delay I_n to Z_n (data sheet: typ 2.9 / 2.8 ns) specparam tlh_i_zn = 2.9; specparam thl_i_zn = 2.8; // Propagation delay I_n to Z (data sheet: typ 4.7 / 4.5 ns) specparam tlh_i_z = 4.7; specparam thl_i_z = 4.5; (s0, s1, s2 => z) = (tlh_s_z, thl_s_z); (s0, s1, s2 => z_n) = (tlh_s_zn, thl_s_zn); (e_n => z) = (tlh_e_z, thl_e_z); (e_n => z_n) = (tlh_e_zn, thl_e_zn); (i0, i1, i2, i3, i4, i5, i6, i7 => z) = (tlh_i_z, thl_i_z); (i0, i1, i2, i3, i4, i5, i6, i7 => z_n) = (tlh_i_zn, thl_i_zn); endspecify endmodule