DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each side) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F253 is a dual 4-input multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (/OE) inputs, allowing the outputs to interface directly with bus oriented systems. o Advanced Schottky process for high speed o Multifunction capability o Non-inverting 3-state outputs
This device contains two identical 4-input multiplexers with 3-state
outputs. They select two bits from four sources selected by common
select inputs (S0, S1). The 4-input multiplexers have individual Output
Enable (/OEa, /OEb) inputs which, when HIGH, force the outputs to a
high impedance (high Z) state. This device is the logic implementation
of a 2-pole, 4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select inputs.
Za = /OEa * ( I0a*/S1*/S0 + I1a*/S1*S0 + I2a*S1*/S0 + I3a*S1*S0 )
Zb = /OEb * ( I0b*/S1*/S0 + I1b*/S1*S0 + I2b*S1*/S0 + I3b*S1*S0 )
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should ensure that Output
Enable signals to 3-state devices whose outputs are tied together are
designed so that there is no overlap.
Pin Function Pin Function --- --------------------------- --- --------------------------- 1 /OEa Side A Output Enable 16 Vcc 2 S1 Common Select 1 15 /OEb Side B Output Enable 3 I3a Side A data input 3 14 S0 Common Select 0 4 I2a Side A data input 2 13 I3b Side B data input 3 5 I1a Side A data input 1 12 I2b Side B data input 2 6 I0a Side A data input 0 11 I1b Side B data input 1 7 Za Side A 3-state output 10 I0b Side B data input 0 8 GND 9 Zb Side B 3-state output
S0 S1 I0 I1 I2 I3 /OE Z -- -- -- -- -- -- --- --- X X X X X X H (Z) L L L X X X L L L L H X X X L H H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H H H X X X L L L H H X X X H L H Address inputs S0 and S1 are common to both sections. H = HIGH voltage level; L = LOW voltage level; X = immaterial; (Z) = high impedance.
Pin Names Description U.L. HIGH/LOW --------- --------------------------------------- ------------- I0a - I3a Side A Data Inputs 0.5 / 0.375 I0b - I3b Side B Data Inputs 0.5 / 0.375 S0, S1 Common Select Inputs 0.5 / 0.375 /OEa Side A Output Enable Input (Active LOW) 0.5 / 0.375 /OEb Side B Output Enable Input (Active LOW) 0.5 / 0.375 Za, Zb 3-State Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units
------ ---------------------------------- --- --- --- -----
Icc Power Supply Current, outputs HIGH 14 20 mA
Icc Power Supply Current, outputs LOW 14 20 mA
Icc Power Supply Current, outputs OFF 14 25 mA
Conditions:
outputs HIGH -- Vcc = Max, /OEn = Gnd; I0, Sn = 4.5 V;
I1 - I3 = Gnd
outputs LOW -- Vcc = Max; I0, Sn, /OEn = Gnd
outputs OFF -- Vcc = Max, /OEn = 4.5 V; I0, Sn = Gnd
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay Sn to Zn 4.0 9.5 13 ns tPHL Propagation Delay Sn to Zn 3.0 8.0 10 ns tPLH Propagation Delay In to Zn 2.0 4.4 6.0 ns tPHL Propagation Delay In to Zn 2.0 4.4 6.0 ns tPZH Output Enable Time 2.0 5.3 7.0 ns tPZL Output Enable Time 2.0 6.5 8.0 ns tPHZ Output Disable Time* 2.0 4.3 6.0 ns tPLZ Output Disable Time* 2.0 4.0 6.0 ns *CL = 5.0 pF
Data sheet transcription as plain text
// ============================================================================ // f253.v — 54F/74F253 Dual 4-Input Multiplexer (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F253.txt (1980 Fairchild FAST Data Book, // pages 4-76 ... 4-78) // // Two 4-input multiplexers with common Select inputs S0, S1 and individual // active-LOW Output Enables (OE_na, OE_nb). A HIGH on an Output Enable // forces the corresponding output to the high impedance state. Outputs // are non-inverting: // // Za = OE_na ? HiZ : selected I_na // Zb = OE_nb ? HiZ : selected I_nb // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f253 ( input wire s0, s1, // common select inputs input wire oe_na, // side A output enable (active LOW) input wire i0a, i1a, i2a, i3a, // side A data inputs 0-3 output wire za, // side A 3-state output input wire oe_nb, // side B output enable (active LOW) input wire i0b, i1b, i2b, i3b, // side B data inputs 0-3 output wire zb // side B 3-state output ); // Selected data inputs (internal nodes), per the truth table: // S1 S0 = binary index into I0..I3 of each side. wire da = s1 ? (s0 ? i3a : i2a) : (s0 ? i1a : i0a); wire db = s1 ? (s0 ? i3b : i2b) : (s0 ? i1b : i0b); assign za = oe_na ? 1'bz : da; assign zb = oe_nb ? 1'bz : db; specify // Propagation delay In to Zn (data sheet: tPLH 2.0/4.4/6.0, // tPHL 2.0/4.4/6.0 ns) specparam tlh_i = 2.0:4.4:6.0; specparam thl_i = 2.0:4.4:6.0; // Propagation delay Sn to Zn (data sheet: tPLH 4.0/9.5/13, // tPHL 3.0/8.0/10 ns) specparam tlh_s = 4.0:9.5:13.0; specparam thl_s = 3.0:8.0:10.0; // Output enable time OE_n to Zn (data sheet: tPZH 2.0/5.3/7.0, // tPZL 2.0/6.5/8.0 ns) specparam tzh = 2.0:5.3:7.0; specparam tzl = 2.0:6.5:8.0; // Output disable time OE_n to Zn, C_L = 5 pF (data sheet: // tPHZ 2.0/4.3/6.0, tPLZ 2.0/4.0/6.0 ns) specparam thz = 2.0:4.3:6.0; specparam tlz = 2.0:4.0:6.0; // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0) (oe_na, i0a, i1a, i2a, i3a => za) = (tlh_i, thl_i, tlz, tzh, thz, tzl); (oe_nb, i0b, i1b, i2b, i3b => zb) = (tlh_i, thl_i, tlz, tzh, thz, tzl); (s0, s1 => za) = (tlh_s, thl_s); (s0, s1 => zb) = (tlh_s, thl_s); endspecify endmodule