DESCRIPTION | FUNCTIONAL DESCRIPTION | CONNECTION DIAGRAM (16-pin DIP) | TRUTH TABLE (each section) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 'F257 is a quad 2-input multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (non-inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (/OE) input, allowing the outputs to interface directly with bus oriented systems. o Multiplexer expansion by tying outputs together o Non-inverting 3-state outputs o Input clamp diodes limit high speed termination effects
The 'F257 selects four bits of data from two sources under control of a
Common Data Select input. When the Select input is LOW, the I0x inputs
are selected; when Select is HIGH, the I1x inputs are selected. The
data on the selected inputs appears at the outputs in true
(non-inverted) form. The device is the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select input.
Za = /OE * ( I1a*S + I0a*/S ) Zb = /OE * ( I1b*S + I0b*/S )
Zc = /OE * ( I1c*S + I0c*/S ) Zd = /OE * ( I1d*S + I0d*/S )
When the Output Enable input (/OE) is HIGH, the outputs are forced to a
high impedance OFF state. If the outputs are tied together, all but
one device must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should ensure the
Output Enable signals to 3-state devices whose outputs are tied
together are designed so there is no overlap.
Pin Function Pin Function --- ----------------------------- --- -------------------------- 1 S Common Data Select input 16 Vcc 2 I0a Source 0, bit a 15 /OE 3-State Output Enable 3 I1a Source 1, bit a 14 I0c Source 0, bit c 4 Za Output a 13 I1c Source 1, bit c 5 I0b Source 0, bit b 12 Zc Output c 6 I1b Source 1, bit b 11 I0d Source 0, bit d 7 Zb Output b 10 I1d Source 1, bit d 8 GND 9 Zd Output d The 3-State Output Enable input /OE (pin 15) is active LOW. Pin-compatible with the 'F157; pin 15 becomes a 3-state Output Enable.
/OE S I0 I1 Z --- - -- -- --- H X X X (Z) L H X L L L H X H H L L L X L L L H X H H = HIGH voltage level; L = LOW voltage level; X = immaterial; (Z) = high impedance.
Pin Names Description U.L. HIGH/LOW --------- ---------------------------------------- ------------- S Common Data Select Input 0.5 / 0.375 /OE 3-State Output Enable Input (Active LOW) 0.5 / 0.375 I0a - I0d Data Inputs from Source 0 0.5 / 0.375 I1a - I1d Data Inputs from Source 1 0.5 / 0.375 Za - Zd Multiplexer Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units
------ ---------------------------------- --- ---- --- -----
Icc Power Supply Current, outputs HIGH 9.0 15 mA
Icc Power Supply Current, outputs LOW 14.5 22 mA
Icc Power Supply Current, outputs OFF 15 23 mA
Conditions:
outputs HIGH -- Vcc = Max; S, I1x = 4.5 V; /OE, I0x = Gnd
outputs LOW -- Vcc = Max; I1x = 4.5 V; /OE, I0x, S = Gnd
outputs OFF -- Vcc = Max; S, I0x = Gnd; /OE, I1x = 4.5 V
Symbol Parameter Min Typ Max Units ------ -------------------------- --- --- --- ----- tPLH Propagation Delay In to Zn 2.0 4.0 6.0 ns tPHL Propagation Delay In to Zn 2.0 3.5 4.5 ns tPLH Propagation Delay S to Zn 4.0 10 13 ns tPHL Propagation Delay S to Zn 3.0 7.5 9.0 ns tPZH Output Enable Time 2.0 5.0 7.0 ns tPZL Output Enable Time 2.0 5.5 7.0 ns tPHZ Output Disable Time* 2.0 4.0 6.0 ns tPLZ Output Disable Time* 2.0 4.0 6.0 ns *CL = 5 pF
Data sheet transcription as plain text
// ============================================================================ // f257.v — 54F/74F257 Quad 2-Input Multiplexer (With 3-State Outputs) // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F257.txt (1980 Fairchild FAST Data Book, // pages 4-79 ... 4-81) // // Four 2-input multiplexers with a Common Data Select input S and a common // active-LOW 3-state Output Enable (OE_n). When S is LOW the I0x inputs // are selected, when HIGH the I1x inputs. Data appears at the outputs in // true (non-inverted) form. A HIGH on OE_n forces all outputs to the high // impedance state. // // Zx = OE_n ? HiZ : (S ? I1x : I0x) // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 15 pF), min:typ:max ns. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f257 ( input wire s, // common data select input input wire oe_n, // 3-state output enable (active LOW) input wire i0a, i1a, // source 0/1 data inputs, bit a output wire za, // output a input wire i0b, i1b, // source 0/1 data inputs, bit b output wire zb, // output b input wire i0c, i1c, // source 0/1 data inputs, bit c output wire zc, // output c input wire i0d, i1d, // source 0/1 data inputs, bit d output wire zd // output d ); assign za = oe_n ? 1'bz : (s ? i1a : i0a); assign zb = oe_n ? 1'bz : (s ? i1b : i0b); assign zc = oe_n ? 1'bz : (s ? i1c : i0c); assign zd = oe_n ? 1'bz : (s ? i1d : i0d); specify // Propagation delay In to Zn (data sheet: tPLH 2.0/4.0/6.0, // tPHL 2.0/3.5/4.5 ns) specparam tlh_i = 2.0:4.0:6.0; specparam thl_i = 2.0:3.5:4.5; // Propagation delay S to Zn (data sheet: tPLH 4.0/10/13, // tPHL 3.0/7.5/9.0 ns) specparam tlh_s = 4.0:10.0:13.0; specparam thl_s = 3.0:7.5:9.0; // Output enable time OE_n to Zn (data sheet: tPZH 2.0/5.0/7.0, // tPZL 2.0/5.5/7.0 ns) specparam tzh = 2.0:5.0:7.0; specparam tzl = 2.0:5.5:7.0; // Output disable time OE_n to Zn, C_L = 5 pF (data sheet: // tPHZ 2.0/4.0/6.0, tPLZ 2.0/4.0/6.0 ns) specparam thz = 2.0:4.0:6.0; specparam tlz = 2.0:4.0:6.0; // 6-delay form, IEEE order (0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0) (oe_n, i0a, i1a => za) = (tlh_i, thl_i, tlz, tzh, thz, tzl); (oe_n, i0b, i1b => zb) = (tlh_i, thl_i, tlz, tzh, thz, tzl); (oe_n, i0c, i1c => zc) = (tlh_i, thl_i, tlz, tzh, thz, tzl); (oe_n, i0d, i1d => zd) = (tlh_i, thl_i, tlz, tzh, thz, tzl); (s => za) = (tlh_s, thl_s); (s => zb) = (tlh_s, thl_s); (s => zc) = (tlh_s, thl_s); (s => zd) = (tlh_s, thl_s); endspecify endmodule