DESCRIPTION | CONNECTION DIAGRAM (14-pin DIP) | TRUTH TABLE (each gate) | INPUT LOADING / FAN-OUT | DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE | AC CHARACTERISTICS | VERILOG MODEL
The 74F86 contains four independent 2-input Exclusive-OR gates in a 14-pin package. Logic function (each gate): Z = A xor B
Pin Function Pin Function --- ------------------- --- ------------------- 1 A1 gate 1 input 14 Vcc 2 B1 gate 1 input 13 B4 gate 4 input 3 Z1 gate 1 output 12 A4 gate 4 input 4 A2 gate 2 input 11 Z4 gate 4 output 5 B2 gate 2 input 10 B3 gate 3 input 6 Z2 gate 2 output 9 A3 gate 3 input 7 GND 8 Z3 gate 3 output
A B Z --- --- --- L L L L H H H L H H H L H = HIGH voltage level; L = LOW voltage level.
Pin Names Description U.L. HIGH/LOW
----------- ------------- -------------
Inputs 0.5 / 0.375
Outputs 25 / 12.5
Symbol Parameter Min Typ Max Units
------ -------------------- --- --- --- -----
ICCL Power Supply Current 18 28 mA
ICCH Power Supply Current 12 18 mA
Conditions: ICCL -- Inputs HIGH; ICCH -- One Input LOW, One Input HIGH.
Vcc = Max.
Symbol Parameter CL Min Typ Max Units ------ ------------------------------------ ----- --- --- --- ----- tPLH Propagation Delay (Other Input LOW) 50 pF 3.0 4.0 5.5 ns tPHL Propagation Delay (Other Input LOW) 50 pF 3.0 4.2 5.5 ns tPLH Propagation Delay (Other Input HIGH) 50 pF 3.5 5.3 7.0 ns tPHL Propagation Delay (Other Input HIGH) 50 pF 3.0 4.7 6.5 ns
Data sheet transcription as plain text
// ============================================================================ // f86.v — 54F/74F86 Quad 2-Input Exclusive-OR Gate // // Fairchild FAST (Advanced Schottky TTL) // Source: docs/devices/54F74F86.txt (1985 Fairchild FAST Data Book, // page 4-30 — the 1980 data book covers the 'F86 in its Section 3 // gate selection guide only). // // Logic function (each gate): Z = A ^ B // // Timing values from the data sheet AC Characteristics table, // 54F/74F column (T_A = +25 C, V_CC = +5.0 V, C_L = 50 pF), min:typ:max ns. // The data sheet specifies each gate twice, once with the other input LOW // and once with it HIGH, so the paths are state dependent: with the other // input LOW the gate passes its input, with it HIGH the gate inverts. // // Ports are scalar and named after the data sheet pin names: Icarus Verilog // does not fully support multi-bit (parallel) specify path connections, so // vector ports would get incorrect per-bit delays. // ============================================================================ `timescale 1ns/100ps module f86 ( input wire a1, b1, // gate 1 inputs output wire z1, // gate 1 output input wire a2, b2, // gate 2 inputs output wire z2, // gate 2 output input wire a3, b3, // gate 3 inputs output wire z3, // gate 3 output input wire a4, b4, // gate 4 inputs output wire z4 // gate 4 output ); assign z1 = a1 ^ b1; assign z2 = a2 ^ b2; assign z3 = a3 ^ b3; assign z4 = a4 ^ b4; specify // Propagation delay, other input LOW (data sheet: tPLH 3.0/4.0/5.5, // tPHL 3.0/4.2/5.5 ns) specparam tlh_lo = 3.0:4.0:5.5; specparam thl_lo = 3.0:4.2:5.5; // Propagation delay, other input HIGH (data sheet: tPLH 3.5/5.3/7.0, // tPHL 3.0/4.7/6.5 ns) specparam tlh_hi = 3.5:5.3:7.0; specparam thl_hi = 3.0:4.7:6.5; if (b1 == 1'b0) (a1 => z1) = (tlh_lo, thl_lo); if (b1 == 1'b1) (a1 => z1) = (tlh_hi, thl_hi); if (a1 == 1'b0) (b1 => z1) = (tlh_lo, thl_lo); if (a1 == 1'b1) (b1 => z1) = (tlh_hi, thl_hi); if (b2 == 1'b0) (a2 => z2) = (tlh_lo, thl_lo); if (b2 == 1'b1) (a2 => z2) = (tlh_hi, thl_hi); if (a2 == 1'b0) (b2 => z2) = (tlh_lo, thl_lo); if (a2 == 1'b1) (b2 => z2) = (tlh_hi, thl_hi); if (b3 == 1'b0) (a3 => z3) = (tlh_lo, thl_lo); if (b3 == 1'b1) (a3 => z3) = (tlh_hi, thl_hi); if (a3 == 1'b0) (b3 => z3) = (tlh_lo, thl_lo); if (a3 == 1'b1) (b3 => z3) = (tlh_hi, thl_hi); if (b4 == 1'b0) (a4 => z4) = (tlh_lo, thl_lo); if (b4 == 1'b1) (a4 => z4) = (tlh_hi, thl_hi); if (a4 == 1'b0) (b4 => z4) = (tlh_lo, thl_lo); if (a4 == 1'b1) (b4 => z4) = (tlh_hi, thl_hi); endspecify endmodule